Function diagram
8
7
6
5
4
3
2
1
fp_mc_787a_e.vsd
Free blocks
MASTERDRIVES MC
02.02.04
Shift register 1 with memory depth 0...49
from V2.2
- 787a -
V2.5
<4> For standard applications it is recommended that the write and read clocks be controlled by a mutual clock pulse.
<5> In the case of "SRx ResetMux" the data and the statuses of the binectors "SR MemDpthFull" und "SR MemDpthOverf" remain.
<6> By means of a correction trigger ("SRx CorrTrigger") the correction value ("SRx CorrValue") is subtracted from the data contents
in the shift register (e.g. can be used for printing index correction).
<7> By means of "SRx EnableData" the contents of the dataset currently being read is transferred to the data output. If the enable does not
take place, the value of connector parameter "SRx Output Value" is switched through to the data output.
On account of the feedback loop (due to factory setting) ("SRx OutputBi" - "SRx EnableData"), when a dataset is being writtten it
is possible with "SRx B0" to define its later validity.
0 = Shift
1 = Ring
Number of datasets corresponds
to "SR MemDpth" + 1
Clock read
Reset (implied upon change of mode or memory depth)
.1
SR1 ClockWrite
SR1 Reset
SR1 ResetMux
SR1 Direction
SR1 CorrTrigger
SR1 EnableData
15
14
7
6
13
12
5
4
11
10
3
2
9
8
1
0
Display of n938.1 on PMU
2
12
2
11
2
10
2
9
2
8
.3
SR1 OutputValue
SR1 CorrValue
SR1 InputKK
<7>
0
MUX
...49
1
Dataset 50
Dataset 49
Dataset 02
Dataset 01
B 0..7
B 0..7
B 0..7
B 0..7
KK
KK
KK
KK
.1
SR1 B0 (Data valid)
SR1 B1
SR1 B2
SR1 B3
SR1 B4
SR1 B5
SR1 B6
SR1 B7
0
MUX
...49
1
0
1
-2
31
+1
2
31
-1
2
0
2
1
2
2
2
3
2
4
2
5
2
6
2
7
<1> "SR MemDpthFull" indicates after reset or power ON
that the shift register is full of data.
<2> "SR MemDpthOverf" indicates that the memory depth
has been run through once.
<3> "SR MemDpthAct" is the actual memory depth that can
deviate from the parameter "SR Mode" if the write/read
clock is controlled separately.
{30µs}
max. memory depth, no-load
{50µs}
max. memory depth, ring buffer
{66µs}
max. memory depth, shift
Acknowledge correction
Acknowledge reset
Internal memory depth
equals zero
Internal memory depth
0
1
0
<8> Data input (1 double-word connector and
8 binectors per dataset)
Priority of input signals (parameters):
Reset > ResetMux > CycleWrite > CycleRead > CorrTrigger
<8>
<7>
<6>
<8>
<7>
<6>
<5>
SR1 ClockRead
<4>
<4>
Clock write
&
&
1
&
&
1
Correction trigger
Reset Multiplexer (only write and read index)
Shift direction (0 = forwards, 1 = backwards)
SR Mode
U933.1 (0)
SR MemDpth
(0...49)
U934.1 (0)
B (0)
U937
Src SR CntrlSig
B (0)
.2
B (0)
.3
B (0)
.4
B (0)
.5
B (0)
.6
B (B0492)
.7
U953.68 = ___(20)
K0495
SR Status (0...12)
B0486
SR CorrAck
SR Status
n938.1
B0488
SR ResetAck
B0595
SR MemDpthFull <1>
B0597
SR MemDpthOverf <2>
B0599
SR MemDpthZero
K0497
SR MemDpthAct (0...49) <3>
KK
U936 (0)
Src SR InputKK
KK
.2
KK
.1
B (1)
U935
Src SR InputBi
B (0)
.2
B (0)
.3
B (0)
.4
B (0)
.5
B (0)
.6
B (0)
.7
B (0)
.8
SR1 RegisterBi
n941.1 ... n941.50
SR1 RegisterKK
n940.1 ... n940.50
B0492
SR1 OutputBi
B0493
B0494
B0495
B0496
B0497
B0498
B0499
KK0499
SR OutputKK
SR OutputKK
n939.1
