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210
High-speed Counters
Section 5-2
sequently, when the Reset Bit is turned ON in the ladder program, the phase-
Z signal does not become effective until the next PLC cycle.
Software Reset
The high-speed counter's PV is reset when the corresponding High-speed
Counter Reset Bit goes from OFF to ON.
The CPU Unit recognizes the OFF-to-ON transition of the High-speed
Counter Reset Bit only at the beginning of the PLC cycle during the oversee-
ing processes. Reset processing is performed at the same time. The OFF-to-
ON transition will not be recognized if the Reset Bit goes OFF again within the
same cycle.
Note The comparison operation can be set to stop or continue when a high-speed
counter is reset. This enables applications where the comparison operation
can be restarted from a counter PV of 0 when the counter is reset.
One cycle
Phase-Z
Reset Bit
PV not
reset
PV not
reset
PV
reset
PV
reset
PV
reset
PV
reset
One cycle
Reset Bit
PV not
reset
PV
reset
PV not
reset
PV not
reset
Summary of Contents for CP1H-CPU - 05-2006
Page 2: ...CP1H X40D CP1H XA40D CP1H Y20DT D CP1H CPU Unit Operation Manual Revised May 2006...
Page 3: ...iv...
Page 11: ...xii TABLE OF CONTENTS...
Page 15: ...xvi...
Page 19: ...xx...
Page 31: ...xxxii Conformance to EC Directives 6...
Page 71: ...40 Function Blocks Section 1 5...
Page 133: ...102 Computing the Cycle Time Section 2 7...
Page 169: ...138 CPM1A Expansion I O Unit Wiring Section 3 6...
Page 411: ...380 Clock Section 6 8...
Page 519: ...488 Replacing User serviceable Parts Section 10 2...
Page 527: ...496 Standard Models Appendix A...
Page 535: ...504 Dimensions Diagrams Appendix B...
Page 628: ...597 Connections to Serial Communications Option Boards Appendix F Connecting to Unit...
Page 629: ...598 Connections to Serial Communications Option Boards Appendix F...
Page 659: ...628 PLC Setup Appendix G...
Page 665: ...634 Index work words 159 write protection 370...
Page 667: ...636 Revision History...