170
Index Registers
Section 4-15
4.
Steps 2 and 3 are processed repeatedly until the conditions are met.
Note
Adding, subtracting incrementing, or decrementing for the Index
Register is performed using one of the following methods.
• Each Type of Indirect Addressing for Index Registers:
Auto-increment (,IR
@
+ or ,IR
@
++), auto-decrement (,-IR
@
or ,--IR
@
),
constant offset (constant ,IR
@
), and DR offset (DR
@
,IR
@
) for Index
Registers
• Instructions for Direct Addressing of Index Registers:
DOUBLE SIGNED BINARY ADD WITHOUT CARRY (+L), DOUBLE
SIGNED BINARY SUBTRACT WITHOUT CARRY (-L), DOUBLE IN-
CREMENT BINARY (++L), DOUBLE DECREMENT BINARY (--L)
Example:
If, for example, instruction A above is a comparison instruction, table data
could be read from start to the end of the table to compare all of the data with
a specific value. In this way, blocks of user-defined processing can be freely
created depending by applying Index Registers.
■
Example Using Index Registers
In the following example, TIM instructions for timer numbers 0 to 99 use set
values in D100 to D109. This can be achieved by using one TIM instruction,
using an index register for the timer number, using another index register for
the Completion Flags, and repeatedly executing the TIM instruction to start
the timers.
Instruction A
Instruction A m+1
Instruction A m+n
MOVR m IR0
The PLC memory address
of address m is stored in IR0.
Repeated execution,
e.g., loop for
FOR or NEXT.
Instruction A ,IR0+
The PLC memory addresses for each T0's PV, Completion
Flag, and W0.00 are set in Index Registers IR0, IR1, and IR2 using a
MOVRW or MOVR instruction.
- The TIM instruction is executed for the timer number
(timer PV) that IR0+ indirectly addresses.
- The Timer Completion Flag that is indirectly addressed for
IR1+ turns ON when the time elapses. When the ON status
is received, bits in the work area that are indirectly
addressed for IR2+ are turned ON.
- The contents of IR0+, IR1+, and IR2+ are automatically
incremented by one after accessing the values using indirect
addressing.
- D0 is incremented.
Repeated
Summary of Contents for CP1H-CPU - 05-2006
Page 2: ...CP1H X40D CP1H XA40D CP1H Y20DT D CP1H CPU Unit Operation Manual Revised May 2006...
Page 3: ...iv...
Page 11: ...xii TABLE OF CONTENTS...
Page 15: ...xvi...
Page 19: ...xx...
Page 31: ...xxxii Conformance to EC Directives 6...
Page 71: ...40 Function Blocks Section 1 5...
Page 133: ...102 Computing the Cycle Time Section 2 7...
Page 169: ...138 CPM1A Expansion I O Unit Wiring Section 3 6...
Page 411: ...380 Clock Section 6 8...
Page 519: ...488 Replacing User serviceable Parts Section 10 2...
Page 527: ...496 Standard Models Appendix A...
Page 535: ...504 Dimensions Diagrams Appendix B...
Page 628: ...597 Connections to Serial Communications Option Boards Appendix F Connecting to Unit...
Page 629: ...598 Connections to Serial Communications Option Boards Appendix F...
Page 659: ...628 PLC Setup Appendix G...
Page 665: ...634 Index work words 159 write protection 370...
Page 667: ...636 Revision History...