Omron CP1H-CPU - 05-2006, Operation Manual

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TR (Temporary Relay) Area
Section 4-12
4-12 TR (Temporary Relay) Area
The TR Area contains 16 bits with addresses ranging from TR0 to TR15.
These temporarily store the ON/OFF status of an instruction block for branch-
ing and are used only with mnemonics. TR bits are useful when there are sev-
eral output branches and interlocks cannot be used.
The TR bits can be used as many times as required and in any order required
as long as the same TR bit is not used twice in the same instruction block.
TR bits can be used only with the OUT and LD instructions. OUT instructions
(OUT TR0 to OUT TR15) store the ON OFF status of a branch point and LD
instructions recall the stored ON OFF status of the branch point.
Forcing Bit Status TR bits cannot be changed from the CX-Programmer.
Examples In this example, a TR bit is used when two outputs have been directly con-
nected to a branch point.
In this example, a TR bit is used when an output is connected to a branch
point without a separate execution condition.
Note A TR bit is not required when there are no execution conditions after the
branch point or there is an execution condition only in the last line of the
instruction block.
LD
OR
OUT
AND
OUT
LD
AND
OUT
0.00
0.01
TR 0
0.02
0.03
TR 0
0.04
0.05
Instruction
Operand
TR0
0.00
0.05
0.01
0.02
0.04
0.03
LD
OUT
AND
OUT
LD
OUT
0.00
TR 0
0.01
0.02
TR 0
0.03
Instruction
Operand
TR0 0.00
0.01 0.02
0.03
LD
0.00
OUT
0.01
AND
OUT
0.02
0.03
LD
0.00
OUT
OUT
0.01
0.02
Instruction Operand
Instruction Operand
0.00
0.01
0.02
0.00 0.01
0.03
0.02