![background image](http://html1.mh-extra.com/html/omron/cp1h-cpu-05-2006/cp1h-cpu-05-2006_operation-manual_742082131.webp)
100
Computing the Cycle Time
Section 2-7
External Interrupt Tasks
The interrupt response time for external interrupt tasks depends on the Unit or
Board (CJ-series Special I/O Unit or CJ-series CPU Bus Unit) that is request-
ing the external interrupt task of the CPU Unit and the type of service
requested by the interrupt. For details, refer to the operation manual for the
Unit or Board being used.
2-7-9
Serial PLC Link Response Performance
The response times for CPU Units connected via a Serial PLC Link (master to
slave or slave to master) can be calculated as shown below. If a PT is in the
Serial PLC Link, however, the amount of communications data will not be
fixed and the values will change.
• Maximum I/O response time (not including hardware delay) =
Master cycle time + Communications cycle time + Slave cycle time + 4 ms
• Minimum I/O response time (not including hardware delay) =
Slave communications time + 1.2 ms
Here,
2-7-10 Pulse Output Start Time
The pulse output start time is the time required from executing a pulse output
instruction until pulses are output externally. This time depends on the pulse
output instruction that is used and operation that is performed.
Software interrupt response time
Internal timer
Scheduled interrupt task
Scheduled interrupt time
Number of partici-
pating slave nodes
The number of slaves to which links have been established
within the maximum unit number set in the master.
Number of non-par-
ticipating slave
nodes
The number of slaves not participating in the links within the
maximum unit number set in the master
Communications
cycle time (ms)
Slave communications time
×
Number of participating slave
nodes + 10
×
Number of non-participating slave nodes
Slave communica-
tions time (ms)
• Communications time set to Standard
24.6 + 0.494
×
((No. of 1)
×
No. of link words
×
2 +
12)
• Communications time set to Fast
25.7 + 0.242
×
((No. of 1)
×
No. of link words
×
2 +
12)
Pulse output instruction
Start time
SPED: continuous
53
µ
s
SPED: independent
55
µ
s
ACC: continuous
65
µ
s
Start time
Instruction execution
Pulse output
Summary of Contents for CP1H-CPU - 05-2006
Page 2: ...CP1H X40D CP1H XA40D CP1H Y20DT D CP1H CPU Unit Operation Manual Revised May 2006...
Page 3: ...iv...
Page 11: ...xii TABLE OF CONTENTS...
Page 15: ...xvi...
Page 19: ...xx...
Page 31: ...xxxii Conformance to EC Directives 6...
Page 71: ...40 Function Blocks Section 1 5...
Page 133: ...102 Computing the Cycle Time Section 2 7...
Page 169: ...138 CPM1A Expansion I O Unit Wiring Section 3 6...
Page 411: ...380 Clock Section 6 8...
Page 519: ...488 Replacing User serviceable Parts Section 10 2...
Page 527: ...496 Standard Models Appendix A...
Page 535: ...504 Dimensions Diagrams Appendix B...
Page 628: ...597 Connections to Serial Communications Option Boards Appendix F Connecting to Unit...
Page 629: ...598 Connections to Serial Communications Option Boards Appendix F...
Page 659: ...628 PLC Setup Appendix G...
Page 665: ...634 Index work words 159 write protection 370...
Page 667: ...636 Revision History...