Supersonic Franky Instruction Manual Download

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Instruction
Manual

Summary of Contents for Franky

Page 2: ...ssor 9 Audio processor 9 Game controller 10 Memory mapper 10 Conversion tool 10 Modifying MSX Bios to reroute VDP output to Franky 14 7 VDP DOCUMENTATION 15 Introduction 15 VDP ports 15 VDP Programming 16 Control port 16 VDP register write 17 Data port 17 Status flags 18 Color RAM 19 Display modes 19 Register reference 21 Patterns 25 Background 25 Horizontal scrolling 25 Vertical scrolling 26 Spri...

Page 3: ...6489 registers 35 Volume registers 36 Tone registers 36 Noise register 36 Example program 37 SN76489 register writes 37 How the SN76489 makes sound 39 Tone channels 40 Noise channel 40 The Linear Feedback Shift Register 41 The external Linear Feedback Shift Register 41 Volume attenuation 42 The imperfect SN76489 43 Playing samples on the PSG 44 Pulse Code Modulation 44 Advanced PCM 45 Pulse Width ...

Page 4: ...to live in Lino Lampers members chello nl mlampers for providing us with the vga connectors and video memory ic s My backyard looked like Zombieland afterwards Bas Kornalijnslijper www bas ditta info for arranging the assembly of our first batch Maxim Zhao www smspower org for helping out in general and for giving us permission to use his texts about the audio part of the Sega A V processors and m...

Page 5: ...e Franky uses his own addresses for accessing the video audio processor Therefore existing Sega homebrew software needs to be converted with our software converter Testing shows that about 75 of programs tested will run without problems after using the converter without any further adjustments This number surely will rise in time when more developers start using Franky We expect more tools useful ...

Page 6: ...ponents So please be gentle when you move or store Franky Besides an MSX Franky also needs a cable to hook up the shared video audio out connector to your monitor or TV This cable is not part of your purchased product package because there are different standards for RGB and CVBS connectors Please check the chapter Technical specifications to examine the pin layout diagram of Franky s output conne...

Page 7: ...input you can choose to connect the MSX to your RGB input and Franky to the CVBS input or vice versa depending on which output possibilities your MSX provides thus eliminating the need for a dual monitor setup Technical specifications Overview Sega A V Processor model 315 5124 or 315 5246 Graphics VDP Video Display Processor derived from Texas Instruments TMS9918 32 simultaneous colors available t...

Page 8: ...in 2 Green Pin 3 Blue Pin 4 Not connected Pin 5 Ground Pin 6 Red ground Pin 7 Green ground Pin 8 Blue ground Pin 9 Not connected Pin 10 Ground Pin 11 Not connected Pin 12 Not connected Pin 13 CVBS Composite output Pin 14 Audio Pin 15 Not connected Please note that although we used a VGA connector for durability you can not use this connector to connect the Franky VDP card to a VGA monitor ...

Page 9: ...ware This reduced our choices of assigning I O addresses while designing Franky To maintain MSX compatibility we have chosen an I O address of H88 for the VDP and H48 for PSG The Franky card itself uses the I O addresses H88 H89 H48 and H49 In the Sega system the game controller uses I O HDC and HDD and if an FM Pac is available it uses HF0 to HF2 All these I O addresses must be changed to run a S...

Page 10: ...ed by writing the page number to memory address HFFFD HFFFE and HFFFF this indicates which 16k part of the rom should be readable at address H0000 H4000 and H8000 In the MSX system the ram memory is mapped the same way but instead of writing the page number to memory the page number is written to I O addresses HFC HFD and HFE Conversion tool This conversion tool loads the ROM image into the MSX me...

Page 11: ... 0E 48 0E 7F 0E 49 0E BE 0E 88 0E BF 0E 89 0E DE No replace 0E DF No replace 0E F0 0E 7C 0E F1 0E 7D 01 7E 01 48 01 7F 01 49 01 BE 01 88 01 BF 01 89 01 DE No replace 01 DF No replace 01 F0 01 7C 01 F1 01 7D D3 7E D3 48 D3 7F D3 49 D3 BE D3 88 D3 BF D3 89 D3 DE No replace D3 DF No replace D3 F0 D3 7C D3 F1 D3 7D ...

Page 12: ...of the found OUT instructions To get full compatibility some points should be implemented as well e g if bit 3 of HFFFC is set an SRAM is mapped at H8000 HBFFF The second game pad needs a subroutine to give the right values when the program reads I O HDD and the detection of the availability of the FM chip is not in the converter as well Code example for disabling the MSX VDP interrupts and adding...

Page 13: ...DP will keep the INT line low so when the Z80 exits the interrupt service routine and enables the interrupt it will jump directly to the ISR again DI LD A HFF All Z80 memory space to the mapper OUT HA8 A LD A HAA Choose sub slot for mapper LD HFFFF A LD A 4 Start of 1st part of 32k rom OUT HFC A LD A 5 2nd part of 32k rom OUT HFD A OUT HFE A JP H0000 Start program 10 IF PEEK HF677 HC0 THEN POKE HF...

Page 14: ...odified BIOS and switch to R800D mode or Z80D As you might know a TR has 64k less memory in DRAM mode because it uses 64k for BIOS in fact the BIOS is mirrored to DRAM while DRAM is much faster This mirror seems to be copied at startup only later on while switching between R800 and R800D only some hardware routes are changed inside the S1990 If we in the meantime update the mirror we get an update...

Page 15: ...d chip built in It is identical to the stand alone version of the same chip VDP ports On MSX the Sega VDP in Franky is commonly accessed at the following Z80 I O ports 48 V counter read SN76489 data write 49 H counter read SN76489 data write mirror 88 Data port r w 89 Control port r w The address decoding for the I O ports is done by the VPD PSG chip with A7 A6 and A0 of the Z80 In Franky the rema...

Page 16: ...after an interrupt routine has executed The VDP has two components that are used for accessing CRAM and VRAM the address register and the code register The address register is 14 bits and defines the address into VRAM for reads and writes and the address into CRAM for writes The code register is 2 bits and selects four different operations VRAM write VRAM read CRAM write and VDP register write The...

Page 17: ...write While the address and code register are updated like normal when a VDP register write is done the command word sent can be viewed as having a different format to the programmer Rxx VDP register number Dxx VDP register data Ignored The VDP selects a register using bits 3 0 of the second byte and writes the data from the first byte to the register in question There are only 10 registers values...

Page 18: ... the first line after the end of the active display period It is cleared when the control port is read For more details see the interrupts section OVR Sprite overflow This flag is set if there are more than eight sprites that are positioned on a single scanline It is cleared when the control port is read For more information see the sprites section COL Sprite collision This flag is set if an opaqu...

Page 19: ... any given time Example Set color 4 to red Display modes The TMS9918 has three bits which select different display modes called M1 M2 and M3 However only four combinations of these bits are documented in the TMS9918 manual The other four undocumented modes are simply variations of the above they are no unique The SMS VDP added another mode select bit that enabled mode 4 which is specific to the SM...

Page 20: ...tion in the name table is not changed If bit 7 of register 0 is set columns 0 23 32 39 can scroll vertically while columns 24 31 do not If bit 6 of register 1 is set rows 0 and 1 will not scroll horizontally Finally setting the horizontal scroll to values of 6 or 7 will cause each tile to be filled with the backdrop color M4 M3 M2 M1 315 5124 315 5246 0 0 0 0 Graphic I Graphic I 0 0 0 1 Text Text ...

Page 21: ... M2 Must be 1 for M1 M3 to change screen height in Mode 4 Otherwise has no effect D0 1 No sync display is monochrome 0 Normal display Setting bit 1 cause the sync information to be lost and gradually the color and picture brightness fade until the display is off Register 01 Mode Control No 2 D7 No effect D6 BLK 1 Display visible 0 display blanked D5 IE0 1 Frame interrupt enable D4 M1 Selects 224 l...

Page 22: ...le column w Low or high byte of name table word x Bits 3 0 of register 2 In all other versions of the VDP bit 0 of register 2 is ignored However the SMS VDP will logically AND bit 0 with the VDP address meaning if bit 0 is cleared bit 4 of the name table row is forced to zero When the screen is displayed this causes the lower 8 rows to mirror the top 16 rows The only game that utilizes this featur...

Page 23: ...No effect Bits 2 0 should be set Otherwise the VDP will fetch pattern data and name table data incorrectly Register 05 Sprite Attribute Table Base Address D7 No effect D6 Bit 13 of the table base address D5 Bit 12 of the table base address D4 Bit 11 of the table base address D3 Bit 10 of the table base address D2 Bit 9 of the table base address D1 Bit 8 of the table base address D0 No effect If bi...

Page 24: ...5 No effect D4 No effect D3 Bit 3 of the overscan color D2 Bit 2 of the overscan color D1 Bit 1 of the overscan color D0 Bit 0 of the overscan color The backdrop color is taken from the sprite palette Register 08 Background X Scroll All eight bits define the horizontal scroll value See the background section for more details Register 09 Background Y Scroll All eight bits define the vertical scroll...

Page 25: ...40 line displays the size of the name table is 32x32 instead Each word in the name table has the following layout Unused Some games use these bits as flags for collision and damage zones such as Wonderboy in Monster Land Zillion 2 p Priority flag When set sprites will be displayed underneath the background pattern in question c Palette select v Vertical flip flag h Horizontal flip flag n Pattern i...

Page 26: ... would be filled with the backdrop color and or sprite pattern data If bit 6 of VDP register 00 is set horizontal scrolling will be fixed at zero for scanlines zero through 15 This is commonly used to create a fixed status bar at the top of the screen for horizontally scrolling games Vertical scrolling Register 09 can be divided into two parts the upper five bits are the starting row and the lower...

Page 27: ... 64 available will not be drawn This only works in the 192 line display mode in the 224 and 240 line modes a Y coordinate of D0 has no special meaning Sprites that are partially off screen when the X coordinate is greater than 248 do not wrap around to the other side of the screen If bit 3 of register 00 is set the X coordinate is treated as being minus eight Sprites that are partially displayed o...

Page 28: ... Perhaps the designers of the SMS VDP forgot to add horizontal zoom flags to the extra four sprites they added which is why only four of the eight sprites are affected Table parsing On each scanline the VDP parses the SAT to find which sprites will be displayed on the next line It goes through each Y coordinate and checks the position along with the sprite height controlled by bit 1 of register 1 ...

Page 29: ...y important from an emulation standpoint I assume the SMS also uses the X coordinate as a down counter Display timing The two basic elements of the VDP are the H and V counters The H counter is incremented with each dot clock Different video related events happen when the H counter reaches certain points At the end of each scanline the V counter is incremented by one and this continues until an en...

Page 30: ...counter values 00 DA D5 FF NTSC 256x224 Lines Description 224 Active display 8 Bottom border 3 Bottom blanking 3 Vertical blanking 13 Top blanking 11 Top border V counter values 00 EA E5 FF NTSC 256x240 This mode does not work on NTSC machines All 30 rows of the name table are displayed there is no border blanking or retrace period and the next frame starts after the 30th row The display rolls con...

Page 31: ...screen areas look like useful if you are emulating overscan or if you want to have a virtual vertical hold control in your emulator Active display Where the display generated by the VDP goes Bottom border Filled with border color from VDP register 7 Bottom blanking Filled with a light black color like display was blanked Vertical sync Filled with a pure black color like display was turned off Top ...

Page 32: ...g Filled with a light black color like display was blanked Horizontal sync Filled with a pure black color like display was turned off Left blanking Filled with border color from VDP register 07 Color burst Filled with a dark brown orange color Left blanking Filled with a light black color like display was blanked Left border Filled with border color from VDP register 07 Currently we don t have inf...

Page 33: ...fter the last line of the active display period To help you understand how this works here is an example for a 192 line display on an NTSC machine that has 262 scanlines per frame Out of lines 0 261 The counter is decremented on lines 0 191 and 192 The counter is reloaded on lines 193 261 When the counter underflows from 00 to FF it is reloaded with the last value written to register 0A Writing to...

Page 34: ...te allows it to give more time to the Z80 Bit 3 of register 00 early clock also affects sprites in the TMS9918 modes by the same amount of 8 pixels In Sean Young s TMS9918 document he describes a problem where the unused bits in some VDP registers that define a table address work like an AND mask over the high order address bits of a pattern index This is the exact same problem that causes the nam...

Page 35: ...s with each 4 bits 3 tone registers consisting of 10 bits and a noise register of 3 bits wide Of course for hardware reasons these may internally be wider The difference between registers is determined by the highest 4 bits SMS PSG 7 6 5 4 3 2 1 0 Byte 0 1 0 0 0 Tune tone A fine Byte 1 0 0 Tune tone A coarse Byte 2 1 0 1 0 Tune tone B fine Byte 3 0 0 Tune tone B coarse Byte 4 1 1 0 0 Tune tone C f...

Page 36: ... lowest bits in X then write 00XXXXXX where X are the 6 highest bits for the tone These 10 bits are calculated as follows X 3579545 32 Desired frequency The CPU clock is internally divided by 32 compared to the MSX PSG the highest 2 bits of the tone are not available The lowest frequency the SMS PSG can make is 109Hz with all 10 bits high Noise register Bit 2 selects the mode periodic or white The...

Page 37: ...ocesses it as follows If bit 7 is 1 then the byte is a LATCH DATA byte Bits 6 and 5 cc give the channel to be latched ALWAYS This selects the row in the above table 00 is channel 0 01 is channel 1 10 is channel 2 11 is channel 3 as you might expect Bit 4 t determines whether to latch volume 1 or tone noise 0 data this gives the column The remaining 4 bits dddd are placed into the low 4 bits of the...

Page 38: ...DDDD update the 4 bit volume value However this is unnecessary Noise register dddd DDDDDD trr trr The low 2 bits of dddd select the shift rate and the next highest bit bit 2 selects the mode white 1 or periodic 0 If a data byte is written its low 3 bits update the shift rate and mode in the same way This means that the following data will have the following effect spacing added for clarity hopeful...

Page 39: ...ch then ignore the data byte will produce the periodic noise which sounds like a high pitched eek instead of a drum beat Many games also produce the above two unusual behaviours but not repeatedly often when a SFX is first played for example Also of note is that the tone registers update immediately when a byte is written they do not wait until all 10 bits are written signifies an unknown bit what...

Page 40: ...by Example values for an NTSC clocked chip are given and are generally assumed throughout Thus for example 0x0fe gives 440 4Hz If the register value is zero or one then the output is a constant value of 1 This is often used for sample playback on the SN76489 Tone range The lowest possible tone using register value 3ff is 109Hz assuming an input clock of 3579545Hz which corresponds to MIDI note A2 ...

Page 41: ...There are two types an external network where the XOR gates are external to the shift register and internal where they are between bits Both are discussed below Certain bits are used as inputs to the XOR gates these are the tapped bits An n bit shift register can generate pseudo random sequences with periodicity up to 2n 1 depending on the tapped bits The external Linear Feedback Shift Register Fo...

Page 42: ...referred to with quotes Volume attenuation The mixer then multiplies each channel s output by the corresponding volume or equivalently applies the corresponding attenuation and sums them The result is output to an amplifier which outputs them at suitable levels for audio The SN76489 attenuates the volume by 2dB for each step in the volume register This is almost completely meaningless to most peop...

Page 43: ...us value was to allow silence to be output Depending on later hardware in the chain between the SN76489 and your ears there may be some distortion introduced My tests with an SMS and a TV card found the highest three volume levels to be clipped for example The imperfect SN76489 Real components aren t perfect The output of the SN76489 in its various implementations can be severely affected by this ...

Page 44: ...y wish to add implementation suggestions Sample playback is possible on the PSG SN76489 but not the YM2413 FM chip It is possible to play samples in two ways Pulse Code Modulation This is the usual way to store process and output waves The data is in the form of voltages corresponding to the desired speaker position which in turn gives corresponding pressure waves in the air which are stored digit...

Page 45: ...save ROM space 136 unique levels are possible 7 1 bits of resolution which seems to be a better trade off By outputting 4 bits to two channels and the other 4 bits to the third the volume range for this 8 bit variation can be boosted at the expense of the uniformity of coverage No known software uses this technique Pulse Width Modulation This works by outputting pulses at constant volume whose pat...

Page 46: ...th a maximum output rate of 20kHz for example one may choose a 6 67kHz 3 bit source sample a 5kHz 4 bit source sample etc This can be severely limiting for the quality Note the output limit 20kHz in this example has yet to be determined for the SMS and will vary depending on how the data is encoded and the playback efficiency On the Master System PWM is not very good quality often the sound is uni...

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