Hitachi H8/326 Series Hardware Manual Download Page 328

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Appendix D. Timing of Transition to and Recovery from

Hardware Standby Mode

Timing of Transition to Hardware Standby Mode

(1) To retain RAM contents with the RAME bit cleared to “0” in SYSCR, drive the RES signal

low 10 system clock cycles before the STBY signal goes low, as shown below. RES must

remain low until STBY goes low (minimum delay from STBY low to RES high: 0 ns).

(2) When the RAME bit in SYSCR is set to “1” or it is not necessary to retain RAM contents, RES

does not have to be driven low as in (1).

Timing of Recovery From Hardware Standby Mode: Drive the RES signal low approximately

100 ns before STBY goes high.

STBY

RES

t 10 t

≥

cyc

t 0 ns

≥

STBY

RES

t 100 ns

≥

OSC

319

Summary of Contents for H8/326 Series

Page 1: ...HITACHI SINGLE CHIP MICROCOMPUTER H8 329 SERIES H8 329 HD6473298 HD6433298 HD6413298 H8 328 HD6433288 H8 327 HD6473278 HD6433278 HD6413278 H8 326 HD6433268 HARDWARE MANUAL OMC942723054 ...

Page 2: ...9 with 32K byte ROM and 1K byte RAM the H8 328 with 24K byte ROM and 1K byte RAM the H8 327 with 16K byte ROM and 512 byte RAM and the H8 326 with 8K byte ROM and 256 byte RAM The H8 329 and H8 327 are available in a masked ROM version a ZTAT Zero Turn Around Time version and a ROMless version providing a quick and flexible response to conditions from ramp up through full scale volume producion ev...

Page 3: ... 19 Section 3 CPU 23 3 1 Overview 23 3 1 1 Features 23 3 2 Register Configuration 24 3 2 1 General Registers 24 3 2 2 Control Registers 25 3 2 3 Initial Register Values 26 3 3 Addressing Modes 27 3 3 1 Addressing Mode 27 3 3 2 How to Calculate Where the Execution Starts 29 3 4 Data Formats 33 3 4 1 Data Formats in General Registers 34 3 4 2 Memory Data Formats 35 3 5 Instruction Set 36 3 5 1 Data ...

Page 4: ...et 59 4 2 1 Overview 59 4 2 2 Reset Sequence 59 4 2 3 Disabling of Interrupts after Reset 62 4 3 Interrupts 62 4 3 1 Overview 62 4 3 2 Interrupt Related Registers 64 4 3 3 External Interrupts 66 4 3 4 Internal Interrupts 67 4 3 5 Interrupt Handling 67 4 3 6 Interrupt Response Time 72 4 3 7 Precaution 72 4 4 Note on Stack Handling 73 Section 5 I O Ports 75 5 1 Overview 75 5 2 Port 1 77 5 3 Port 2 8...

Page 5: ...30 6 4 2 Output Compare Timing 132 6 4 3 Input Capture Timing 133 6 4 4 Setting of FRC Overflow Flag OVF 136 6 5 Interrupts 137 6 6 Sample Application 137 6 7 Application Notes 138 Section 7 8 Bit Timers 143 7 1 Overview 143 7 1 1 Features 143 7 1 2 Block Diagram 143 7 1 3 Input and Output Pins 144 7 1 4 Register Configuration 145 7 2 Register Descriptions 145 7 2 1 Timer Counter TCNT H FFCC TMR0 ...

Page 6: ... Data Register TDR H FFDB 167 8 2 5 Serial Mode Register SMR H FFD8 167 8 2 6 Serial Control Register SCR H FFDA 170 8 2 7 Serial Status Register SSR H FFDC 174 8 2 8 Bit Rate Register BRR H FFD9 177 8 2 9 Serial Timer Control Register STCR H FFC3 181 8 3 Operation 182 8 3 1 Overview 182 8 3 2 Asynchronous Mode 184 8 3 3 Clocked Synchronous Operation 197 8 4 SCI Interrupts 206 8 5 Application Note...

Page 7: ... 11 1 Overview 227 11 1 1 Block Diagram 228 11 2 PROM Mode H8 329 H8 327 228 11 2 1 PROM Mode Setup 228 11 2 2 Socket Adapter Pin Assignments and Memory Map 229 11 3 Programming 232 11 3 1 Writing and Verifying 232 11 3 2 Notes on Writing 236 11 3 3 Reliability of Written Data 236 11 3 4 Erasing of Data 237 11 4 Handling of Windowed Packages 238 Section 12 Power Down State 239 12 1 Overview 239 12...

Page 8: ...m Ratings 251 14 2 Electrical Characteristics 251 14 2 1 DC Characteristics 251 14 2 2 AC Characteristics 257 14 2 3 A D Converter Characteristics 261 14 3 MCU Operational Timing 262 14 3 1 Bus Timing 262 14 3 2 Control Signal Timing 263 14 3 3 16 Bit Free Running Timer Timing 266 14 3 4 8 Bit Timer Timing 267 14 3 5 Serial Communication Interface Timing 268 14 3 6 I O Port Timing 269 Appendices A...

Page 9: ...Appendix C Pin States 317 C 1 Pin States in Each Mode 317 Appendix D Timing of Transition to and Recovery from Hardware Standby Mode 319 Appendix E Package Dimensions 320 vii ...

Page 10: ...figurations These include ROM RAM two types of timers a 16 bit free running timer and 8 bit timers a serial communication interface SCI an A D converter and I O ports The H8 329 Series can operate in a single chip mode or in two expanded modes depending on the requirements of the application The operating mode will be referred to as the MCU mode in this manual The entire H8 329 Series is available...

Page 11: ...s 8 bits Bit accumulator instructions Register indirect specification of bit positions Memory H8 329 32k byte ROM 1k byte RAM H8 328 24k byte ROM 1k byte RAM H8 327 16k byte ROM 512 byte RAM H8 326 8k byte ROM 256 byte RAM 16 bit free One 16 bit free running counter can also count external events running timer Two output compare lines 1 channel Four input capture lines can be buffered 8 bit timer ...

Page 12: ...ports 43 input output lines 16 of which can drive LEDs 8 input only lines Interrupts Four external interrupt lines NMI IRQ0 IRQ1 IRQ2 18 on chip interrupt sources Operating Expanded mode with on chip ROM disabled mode 1 modes Expanded mode with on chip ROM enabled mode 2 Single chip mode mode 3 Power down Sleep mode modes Software standby mode Hardware standby mode Other features On chip oscillato...

Page 13: ...328 HD6433288P HD6433288VP 64 pin shrink DIP DP 64S Masked ROM HD6433288F HD6433288VF 64 pin QFP FP 64A HD6433288CP HD6433288VCP 68 pin PLCC CP 68 H8 327 HD6473278C HD6473278VC 64 pin windowed shrink DIP PROM DC 64S HD6473278P HD6473278VP 64 pin shrink DIP DP 64S HD6473278F HD6473278VF 64 pin QFP FP 64A HD6473278CP HD6473278VCP 68 pin PLCC CP 68 HD6433278P HD6433278VP 64 pin shrink DIP DP 64S Mask...

Page 14: ... A5 P16 A6 P17 A7 RES MD 1 MD 0 V CC STBY NMI V CC V SS V SS V SS V SS V SS V SS XTAL EXTAL P4 IRQ ADTRG P4 IRQ P4 IRQ P4 RD P4 WR P4 AS P4 Ø P4 WAIT 1 2 0 1 2 3 4 5 6 7 2 1 0 Notes Memory Sizes H8 328 24k bytes 1k byte H8 327 16k bytes 512 bytes H8 326 8k bytes 256 bytes ROM RAM 1 2 CP 68 package only PROM is available only in the H8 329 and H8 327 H8 329 32k bytes 1k byte Data bus High Address b...

Page 15: ...64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 P40 ADTRG IRQ2 P41 IRQ1 P42 IRQ0 P43 RD P44 WR P45 AS P46 Ø P47 WAIT P50 TxD P51 RxD P52 SCK RES NMI VCC STBY VSS XTAL EXTAL MD1 MD0 AVSS P70 AN0 P71 AN1 P72 AN2 P73 AN3 P74 AN4 P75 AN5 P76 AN6 P77 AN7 AVCC P60 FTCI TMCI0 P61 FTOA P37 D7 P36 D6 P35 D5 P34 D4 P33 D3 P32 D2 P31 D1 P30 D0 P10 A0 P11 A1 P12...

Page 16: ...3 AN 3 P7 4 AN 4 P7 5 AN 5 P7 6 AN 6 P7 7 AN 7 AV CC P6 0 FTCI TMCI 0 P6 1 FTOA P6 2 FTIA P6 3 FTIB TMRI 0 P6 4 FTIC TMO 0 P6 5 FTID TMCI 1 P6 6 FTOB TMRI 1 P6 7 TMO 1 V CC P2 7 A 15 P50 TxD P51 RxD P52 SCK RES NMI VCC STBY VSS XTAL EXTAL MD1 MD0 AVSS P70 AN0 P71 AN1 P72 AN2 P10 A0 P11 A1 P12 A2 P13 A3 P14 A4 P15 A5 P16 A6 P17 A7 VSS P20 A8 P21 A9 P22 A10 P23 A11 P24 A12 P25 A13 P26 A14 17 18 19 2...

Page 17: ... P7 3 AN 3 P7 4 AN 4 P7 5 AN 5 P7 6 AN 6 P7 7 AN 7 AV CC P6 0 FTCI TMCI 0 P6 1 FTOA V SS P6 2 FTIA P6 3 FTIB TMRI 0 P6 4 FTIC TMO 0 P6 5 FTID TMCI 1 P6 6 FTOB TMRI 1 P6 7 TMO 1 V CC P2 7 A 15 P50 TxD P51 RxD P52 SCK RES NMI VCC STBY VSS VSS XTAL EXTAL MD1 MD0 AVSS P70 AN0 P71 AN1 P72 AN2 P10 A0 P11 A1 P12 A2 P13 A3 P14 A4 P15 A5 P16 A6 P17 A7 VSS VSS P20 A8 P21 A9 P22 A10 P23 A11 P24 A12 P25 A13 P...

Page 18: ...NC 9 1 10 P50 TxD P50 TxD P50 TxD NC 10 2 11 P51 RxD P51 RxD P51 RxD NC 11 3 12 P52 SCK P52 SCK P52 SCK NC 12 4 13 RES RES RES VPP 13 5 14 NMI NMI NMI EA9 14 6 15 VCC VCC VCC VCC 15 7 16 STBY STBY STBY VSS 16 8 17 VSS VSS VSS VSS 18 VSS VSS VSS VSS 17 9 19 XTAL XTAL XTAL NC 18 10 20 EXTAL EXTAL EXTAL NC 19 11 21 MD1 MD1 MD1 VSS 20 12 22 MD0 MD0 MD0 VSS 21 13 23 AVSS AVSS AVSS VSS 22 14 24 P70 AN0 ...

Page 19: ...31 42 VCC VCC VCC VCC 40 32 43 A15 A27 A15 P27 CE 41 33 44 A14 P26 A14 P26 EA14 42 34 45 A13 P25 A13 P25 EA13 43 35 46 A12 P24 A12 P24 EA12 44 36 47 A11 P23 A11 P23 EA11 45 37 48 A10 P22 A10 P22 EA10 46 38 49 A9 P21 A9 P21 OE 47 39 50 A8 P20 A8 P20 EA8 48 40 51 VSS VSS VSS VSS 52 VSS VSS VSS VSS 49 41 53 A7 P17 A7 P17 EA7 50 42 54 A6 P16 A6 P16 EA6 51 43 55 A5 P15 A5 P15 EA5 52 44 56 A4 P14 A4 P14...

Page 20: ...external clock is input at the EXTAL pin a reverse phase clock should be input at the XTAL pin EXTAL 18 10 20 I External crystal Connected to a crystal oscillator or external clock The frequency of the external clock should be double the desired system clock frequency See section 13 2 Oscillator Circuit for examples of connections to a crystal and external clock Ø 7 63 8 O System clock Supplies th...

Page 21: ... Strobe Goes Low to indicate that there is a valid address on the address bus Interrupt NMI 13 5 14 I NonMaskable Interrupt Highest signals priority interrupt request The NMIEG bit in the system control register SYSCR determines whether the interrupt is requested on the rising or falling edge of the NMI input IRQ0 to 1 to 3 57 to 59 2 to 4 I Interrupt Request 0 to 2 Maskable IRQ2 interrupt request...

Page 22: ...9 I FRT Input capture A to D Input capture FTID pins for the free running timer 8 bit TMO0 35 27 38 O 8 bit TiMer Output Compare match timer TMO1 38 30 41 output pins for the 8 bit timers TMCI0 31 23 33 I 8 bit TiMer counter Clock Input TMCI1 36 28 39 External clock input pins for the 8 bit timer counters TMRI0 34 26 37 I 8 bit TiMer counter Reset Input TMRI1 37 29 40 A High input at these pins re...

Page 23: ...r P2DDR P37 to P30 57 to 64 49 to 56 61 to 68 I O Port 3 An 8 bit input output port with programmable MOS input pull ups The direction of each bit can be selected in the port 3 data direction register P3DDR P47 to P40 1 to 8 57 to 64 2 to 9 I O Port 4 An 8 bit input output port The direction of each bit can be selected in the port 4 data direction register P4DDR P52 to P50 9 to 11 1 to 3 10 to 12 ...

Page 24: ...ow Mode 1 Low High Expanded Disabled Enabled Mode 2 High Low Expanded Enabled Enabled Mode 3 High High Single chip Enabled Enabled Note If the RAME bit in the system control register SYSCR is cleared to 0 off chip memory can be accessed instead Modes 1 and 2 are expanded modes that permit access to off chip memory and peripheral devices The maximum address space supported by these externally expan...

Page 25: ...ter SYSCR H FFC4 Bit 7 6 5 4 3 2 1 0 SSBY STS2 STS1 STS0 NMIEG RAME Initial value 0 0 0 0 1 0 1 1 Read Write R W R W R W R W R W R W The system control register SYSCR is an 8 bit register that controls the operation of the chip Bit 7 Software Standby SSBY Enables transition to the software standby mode For details see section 12 Power Down State On recovery from software standby mode by an externa...

Page 26: ... 0 0 1 Settling time 16384 states 0 1 0 Settling time 32768 states 0 1 1 Settling time 65536 states 1 Settling time 131072 states Bit 3 Reserved This bit cannot be modified and is always read as 1 Bit 2 NMI Edge NMIEG Selects the valid edge of the NMI input Bit 2 NMIEG Description 0 An interrupt is requested on the falling edge of the NMI input Initial value 1 An interrupt is requested on the risi...

Page 27: ...d are always read as 1 Bits 4 and 3 Reserved These bits cannot be modified and are always read as 0 Bit 2 Reserved This bit cannot be modified and is always read as 1 Bits 1 and 0 Mode Select 1 and 0 MDS1 and MDS0 These bits indicate the values of the mode pins MD1 and MD0 thus indicating the current operating mode of the chip MDS1 corresponds to MD1 and MDS0 to MD0 These bits can be read but not ...

Page 28: ...H 0000 Mode 1 Expanded Mode without On Chip ROM Mode 2 Expanded Mode with On Chip ROM Mode 3 Single Chip Mode Vector Table On Chip ROM 32k bytes Vector Table Vector Table External Address Space On Chip RAM 1k byte On Chip RAM 1k byte External Address Space External Address Space External Address Space On Chip RAM 1k byte On Chip Register Field On Chip Register Field On Chip Register Field External...

Page 29: ...ip ROM Mode 3 Single Chip Mode Vector Table On Chip ROM 24k bytes Vector Table Vector Table Reserved 1 External Address Space On Chip RAM 2 1k byte On Chip RAM 1k byte External Address Space External Address Space External Address Space On Chip RAM 2 1k byte On Chip Register Field On Chip Register Field On Chip Register Field Do not access these reserved areas External memory can be accessed at th...

Page 30: ... ROM Mode 3 Single Chip Mode Vector Table On Chip ROM 16k bytes Vector Table Vector Table Reserved 1 Reserved 1 2 Reserved 1 2 External Address Space On Chip RAM 2 512 Bytes On Chip RAM 512 Bytes External Address Space External Address Space External Address Space On Chip RAM 2 512 Bytes On Chip Register Field On Chip Register Field On Chip Register Field Do not access these reserved areas Externa...

Page 31: ...p ROM Mode 3 Single Chip Mode Vector Table On Chip ROM 8k bytes Vector Table Vector Table Reserved 1 Reserved 1 2 Reserved 1 2 External Address Space On Chip RAM 2 256 Bytes On Chip RAM 256 Bytes External Address Space External Address Space External Address Space On Chip RAM 2 256 Bytes On Chip Register Field On Chip Register Field On Chip Register Field Do not access these reserved areas Externa...

Page 32: ...ructions including Multiply and divide instructions Powerful bit manipulation instructions Eight addressing modes Register direct Rn Register indirect Rn Register indirect with displacement d 16 Rn Register indirect with post increment or pre decrement Rn or Rn Absolute address aa 8 or aa 16 Immediate xx 8 or xx 16 PC relative d 8 PC Memory indirect aa 8 Maximum 64K byte address space High speed o...

Page 33: ...t registers or the high and low bytes can be accessed separately as 8 bit registers R0H to R7H and R0L to R7L R7 also functions as the stack pointer used implicitly by hardware in processing interrupts and subroutine calls In assembly language coding R7 can also be denoted by the letters SP As indicated in figure 3 2 R7 SP points to the top of the stack 0 7 R0H R0L R1H R1L R2H R2L R3L R3H R4L R4H ...

Page 34: ...upt Mask Bit I When this bit is set to 1 all interrupts except NMI are masked This bit is set to 1 automatically by a reset and at the start of interrupt handling Bit 6 User Bit U This bit can be written and read by software using the LDC STC ANDC ORC and XORC instructions Bit 5 Half Carry Flag H This flag is set to 1 when the ADD B ADDX B SUB B SUBX B NEG B or CMP B instruction causes a carry or ...

Page 35: ... bit Bit manipulation and bit load instructions as a bit accumulator The LDC STC ANDC ORC and XORC instructions enable the CPU to load and store the CCR and to set or clear selected bits by logic operations The N Z V and C flags are used in conditional branching instructions BCC For the action of each instruction on the flag bits see the H8 300 Series Programming Manual 3 2 3 Initial Register Valu...

Page 36: ...U 8 bits 8 bits and DIVXU 16 bits 8 bits instructions have 16 bit operands 2 Register indirect Rn The register field of the instruction specifies a 16 bit general register containing the address of the operand 3 Register Indirect with Displacement d 16 Rn This mode which is used only in MOV instructions is similar to register indirect but the instruction has a second word bytes 3 and 4 which is ad...

Page 37: ...s third and fourth bytes Only MOV W instructions can contain 16 bit immediate values The ADDS and SUBS instructions implicitly contain the value 1 or 2 as immediate data Some bit manipulation instructions contain 3 bit immediate data xx 3 in the second or fourth byte of the instruction specifying a bit number 7 Program Counter Relative d 8 PC This mode is used to generate branch addresses in the B...

Page 38: ...AND OR XOR are used In the move instruction 7 program counter relative and 8 all addressing mode to delete the memory indirect can be used In the bit manipulation instruction for the operand specifications 1 register direct 2 register indirect as well as 5 absolute address 8 bit can be used Furthermore to specify the bit number within the operand 1 register direct for each instruction BSET BCLR BN...

Page 39: ...6 bit register contents 0 15 Register indirect with displacement d 16 Rn op regm regn 8 7 3 4 0 15 op reg 7 6 3 4 0 15 disp op reg 7 6 3 4 0 15 Register indirect with post increment Rn op reg 7 6 3 4 0 15 Register indirect with pre decrement Rn 2 3 4 1 for a byte operand 2 for a word operand 0 15 disp 0 15 0 15 0 15 1 or 2 0 15 0 15 1 or 2 0 15 regm 3 0 regn 3 0 16 bit register contents 16 bit reg...

Page 40: ...tive address calculation Effective address 5 Absolute address aa 8 Operand is 1 or 2 byte immediate data aa 16 op 8 7 0 15 op 0 15 IMM op disp 7 0 15 PC relative d 8 PC 6 7 0 15 PC contents 0 15 0 15 abs H FF 8 7 0 15 0 15 abs op xx 16 op 8 7 0 15 IMM Immediate xx 8 8 Sign extension disp 31 ...

Page 41: ...d instruction format No Effective address calculation Effective address 8 Memory indirect aa 8 op 8 7 0 15 Memory contents 16 bits 0 15 abs H 00 8 7 0 15 Notation reg op disp IMM abs General register Operation code Displacement Immediate data Absolute address 32 ...

Page 42: ...0 1 2 7 in a byte operand All arithmetic and logic instructions except ADDS and SUBS can operate on byte data The DAA and DAS instruction perform decimal arithmetic adjustments on byte data in packed BCD form Each nibble of the byte is treated as a decimal digit The MOV W ADD W SUB W CMP W ADDS SUBS MULXU 8 bits 8 bits and DIVXU 16 bits 8 bits instructions operate on word data 33 ...

Page 43: ...l register MSB Most significant bit LSB Least significant bit 4 Bit BCD data 1 Bit data 1 Bit data Byte data Byte data Word data 4 Bit BCD data Data type RnL RnH RnL RnH RnL Rn RnH Register No Don t care 4 3 7 0 Data format 7 0 7 6 5 4 3 2 1 0 Don t care Don t care 7 6 5 4 3 2 1 0 Don t care 7 0 Don t care 7 0 0 15 Don t care 4 3 7 0 7 0 M S B L S B M S B L S B Upper digit Lower digit Upper digit ...

Page 44: ...e vector table Figure 3 4 Memory Data Formats When the stack is addressed using R7 it must always be accessed a word at a time When the CCR is pushed on the stack two identical copies of the CCR are pushed to make a complete word When they are returned the lower byte is ignored 7 0 7 6 5 4 3 2 1 0 1 Bit data Byte data Word data Byte data CCR on stack Word data on stack Data type Data format Addres...

Page 45: ...in each category and indicate the bit patterns of their object code The notation used is defined next Function Instructions Types Data transfer MOV MOVTPE 3 MOVFPE 3 PUSH 1 POP 1 3 Arithmetic operations ADD SUB ADDX SUBX INC DEC ADDS SUBS 14 DAA DAS MULXU DIVXU CMP NEG Logic operations AND OR XOR NOT 4 Shift SHAL SHAR SHLL SHLR ROTL ROTR ROTXL 8 ROTXR Bit manipulation BSET BCLR BNOT BTST BAND BIAN...

Page 46: ... PC Program counter CCR Condition code register N N negative flag of CCR Z Z zero flag of CCR V V overflow flag of CCR C C carry flag of CCR imm Immediate data xx 3 3 Bit immediate data xx 8 8 Bit immediate data xx 16 16 Bit immediate data disp Displacement Addition Subtraction Multiplication Division AND logical OR logical Exclusive OR logical Move Not 37 ...

Page 47: ...mmediate data to a general register The Rn Rn d 16 Rn aa 16 xx 8 or xx 16 Rn and Rn addressing modes are available for byte or word data The aa 8 addressing mode is available for byte data only The R7 and R7 modes require word operands Do not specify byte size for these two modes MOVTPE B Not supported by the H8 329 Series MOVFPE B Not supported by the H8 329 Series PUSH W Rn SP Pushes a 16 bit ge...

Page 48: ...n d 16 Rm Rm Rn or Rn Rm abs aa 8 Rn or Rn aa 8 aa 16 Rn or abs Rn aa 16 r imm xx 8 Rn xx 16 Rn imm r MOVFPE MOVTPE abs m n r r m n rn n rn n Op Op Op Op Op Op Op Op rn Op PUSH POP r r m n r r m n rn Op Op Operation field rm rn Register field disp Displacement abs Absolute address imm Immediate data 39 ...

Page 49: ...ediate data and data in a general register INC B Rd 1 Rd DEC Increments or decrements a general register ADDS W Rd imm Rd SUBS Adds or subtracts immediate data to or from data in a general register The immediate data must be 1 or 2 DAA B Rd decimal adjust Rd DAS Decimal adjusts adjusts to packed BCD an addition or subtraction result in a general register by referring to the CCR MULXU B Rd Rs Rd Pe...

Page 50: ...and another general register or immediate data OR B Rd Rs Rd Rd imm Rd Performs a logical OR operation on a general register and another general register or immediate data XOR B Rd Rs Rd Rd imm Rd Performs a logical exclusive OR operation on a general register and another general register or immediate data NOT B Rd Rd Obtains the one s complement logical complement of general register contents Ins...

Page 51: ...UB CMP ADDX SUBX Rm MULXU DIVXU Op ADDS SUBS INC DEC DAA DAS NEG NOT Op imm ADD ADDX SUBX CMP xx 8 AND OR XOR Rm imm AND OR XOR xx 8 SHAL SHAR SHLL SHLR ROTL ROTR ROTXL ROTXR Op Op Op Op rm rn rn rn rm rn rn rn Op Operation field rm rn Register field imm Immediate data 42 ...

Page 52: ...y a bit number given in 3 bit immediate data or the lower three bits of a general register BTST B bit No of EAd Z Tests a specified bit in a general register or memory and sets or clears the Z flag accordingly The bit is specified by a bit number given in 3 bit immediate data or the lower three bits of a general register BAND B C bit No of EAd C ANDs the C flag with a specified bit in a general re...

Page 53: ... Function BIXOR B C bit No of EAd C XORs the C flag with the inverse of a specified bit in a general register or memory The bit number is specified by 3 bit immediate data BLD B bit No of EAd C Copies a specified bit in a general register or memory to the C flag BILD bit No of EAd C Copies the inverse of a specified bit in a general register or memory to the C flag The bit number is specified by 3...

Page 54: ... FE Finally the CPU writes this value H FE back to P4DDR to complete the BCLR instruction As a result P40DDR is cleared to 0 making P40 an input pin In addition P47DDR and P46DDR are set to 1 making P47 and P46 output pins P47 P46 P45 P44 P43 P42 P41 P40 Input output Input Input Output Output Output Output Output Output Pin state Low High Low Low Low Low Low Low DDR 0 0 1 1 1 1 1 1 DR 1 0 0 0 0 0 ...

Page 55: ... No immediate xx 3 n Op Op abs Operand absolute aa 8 imm 0 0 0 0 Bit No immediate xx 3 Op Op r 0 0 0 0 Operand register indirect Rn imm 0 0 0 0 Bit No immediate xx 3 n Op Op BAND BOR BXOR BLD BST imm Operand register direct Rn Bit No immediate xx 3 r n Op BIAND BIOR BIXOR BILD BIST imm Operand register direct Rn Bit No immediate xx 3 rn Op abs Operand absolute aa 8 0 0 0 0 Bit No immediate xx 3 im...

Page 56: ... Same C Z 1 BCC BHS 0 1 0 0 Carry Clear C 0 High or Same BCS BLO 0 1 0 1 Carry Set Low C 1 BNE 0 1 1 0 Not Equal Z 0 BEQ 0 1 1 1 Equal Z 1 BVC 1 0 0 0 Overflow Clear V 0 BVS 1 0 0 1 Overflow Set V 1 BPL 1 0 1 0 Plus N 0 BMI 1 0 1 1 Minus N 1 BGE 1 1 0 0 Greater or Equal N V 0 BLT 1 1 0 1 Less Than N V 1 BGT 1 1 1 0 Greater Than Z N V 0 BLE 1 1 1 1 Less or Equal Z N V 1 JMP Branches unconditionally...

Page 57: ... 7 0 cc disp Bcc 0 0 0 0 JMP Rm JMP aa 16 abs abs JMP aa 8 disp BSR r 0 0 0 0 JSR Rm JSR aa 16 abs JSR aa 8 RTS m rm Op Op Op Op Op Op Op Op abs Op Op Operation field cc Condition field rm Register field disp Displacement abs Absolute address 48 ...

Page 58: ...R imm CCR Moves immediate data or general register contents to the condition code register STC B CCR Rd Copies the condition code register to a specified general register ANDC B CCR imm CCR Logically ANDs the condition code register with immediate data ORC B CCR imm CCR Logically ORs the condition code register with immediate data XORC B CCR imm CCR Logically exclusive ORs the condition code regis...

Page 59: ...NOP Op r LDC STC Rn imm ANDC ORC XORC LDC xx 8 n Op Op Op Operation field rn Register field imm Immediate data Instruction Size Function EEPMOV if R4L 0 then repeat R5 R6 R4L 1 R4L until R4L 0 else next Moves a data block according to parameters set in general registers R4L R5 and R6 R4L size of block bytes R5 starting source address R6 starting destination address Execution of the next instructio...

Page 60: ...er down state The power down state is further divided into three modes the sleep mode software standby mode and hardware standby mode Figure 3 11 summarizes these states and figure 3 12 shows a map of the state transitions Figure 3 11 Operating States 15 8 7 0 Op Op EEPROM State Program execution state The CPU executes successive program instructions Exception handling state A transient state trig...

Page 61: ...sk I bit in the condition code register to 1 3 Fetches the start address of the exception handling routine from the vector table 4 Branches to that address returning to the program execution state See section 4 Exception Handling for further information on the exception handling state Reset state Hardware standby mode SLEEP instruction Interrupt request RES 1 Power down state Sleep mode Exception ...

Page 62: ... Hardware Standby Mode The hardware standby mode is entered when the input at the STBY pin goes Low All chip functions halt including I O port output The on chip supporting modules are initialized but on chip RAM contents are held See section 12 Power Down State for further information 3 7 Access Timing and Bus Cycle The CPU is driven by the system clock Ø The period from one rising edge of the sy...

Page 63: ...ccess Cycle Bus cycle T1 state T2 state Internal address bus Address Write data Internal Read signal Internal data bus read Read data Internal Write signal Internal data bus write Ø T2 state Bus cycle T1 state Ø Address bus Address Data bus high impedance state AS High RD High WR High 54 ...

Page 64: ...s to word data or instruction codes requires two consecutive cycles six states Figure 3 15 shows the access cycle for the on chip register field Figure 3 16 shows the associated pin states Figures 3 17 a and b show the read and write access timing for external devices Figure 3 15 On Chip Register Field Access Cycle Write data Bus cycle T1 state T2 state T3 state Internal address bus Ø Address Inte...

Page 65: ...ycle Figure 3 17 a External Device Access Timing Read Bus cycle T1 state T2 state T3 state Address bus Ø Address AS High RD High WR High Data bus high impedance state Read cycle T1 state T2 state T3 state Address bus Ø Address Read data AS RD WR High Data bus 56 ...

Page 66: ...Figure 3 17 b External Device Access Timing Write Write cycle T1 state T2 state T3 state Address bus Ø Address Write data AS RD High WR Data bus 57 ...

Page 67: ...58 ...

Page 68: ...current hardware exception handling sequence 4 2 Reset 4 2 1 Overview A reset has the highest exception handling priority When the RES pin goes Low all current processing stops and the chip enters the reset state The internal state of the CPU and the registers of the on chip supporting modules are initialized When RES returns from Low to High the reset exception handling sequence starts 4 2 2 Rese...

Page 69: ...eld Low when power is switched off as well as when power is switched on Figure 4 1 indicates the timing of the reset sequence in modes 2 and 3 Figure 4 2 indicates the timing in mode 1 Figure 4 1 Reset Sequence Mode 2 or 3 Program Stored in On Chip ROM 1 2 3 Ø RES 2 Internal address bus Internal Read signal Internal Write signal Internal data bus 16 bits 1 Reset vector address H 0000 2 Starting ad...

Page 70: ...ram contents of reset vector 2 upper byte 4 lower byte 5 7 Starting address of program 5 2 4 7 2 4 1 6 8 First instruction of program 6 first byte 8 second byte Vector fetch Internal process ing Instruction prefetch RES D7 to D0 8 bits A15 to A0 Ø RD WR Figure 4 2 Reset Sequence Mode 1 61 ...

Page 71: ...p supporting modules Table 4 2 lists the interrupt sources in priority order and gives their vector addresses When two or more interrupts are requested the interrupt with highest priority is served first The features of these interrupts are NMI has the highest priority and is always accepted All internal and external interrupts except NMI can be masked by the I bit in the CCR When the I bit is set...

Page 72: ... H 0024 H 0025 8 Bit timer 0 CMI0A Compare match A 19 H 0026 H 0027 CMI0B Compare match B 20 H 0028 H 0029 OVI0 Overflow 21 H 002A H 002B 8 Bit timer 1 CMI1A Compare match A 22 H 002C H 002D CMI1B Compare match B 23 H 002E H 002F OVI1 Overflow 24 H 0030 H 0031 Reserved 25 H 0032 H 0033 26 H 0034 H 0035 Serial ERI Receive error 27 H 0036 H 0037 communication RXI Receive end 28 H 0038 H 0039 interfa...

Page 73: ...d Write R W R W R W R W R W R W The valid edge on the NMI line is controlled by bit 2 NMIEG in the system control register Bit 2 NMI Edge NMIEG Determines whether a nonmaskable interrupt is generated on the falling or rising edge of the NMI input signal Bit 2 NMIEG Description 0 An interrupt is generated on the falling edge of NMI Initial state 1 An interrupt is generated on the rising edge of NMI...

Page 74: ...to IRQ2 interrupts individually Bits 0 to 2 IRQ0E to IRQ2E Description 0 IRQ0 to IRQ2 interrupt requests are disabled Initial state 1 IRQ0 to IRQ2 interrupt requests are enabled When edge sensing is selected by setting bits IRQ0SC to IRQ7SC to 1 it is possible for an interrupt handling routine to be executed even though the corresponding enable bit IRQ0E to IRQ7E is cleared to 0 and the interrupt ...

Page 75: ...ether the I interrupt mask bit is set in the CCR The valid edge is selected by the NMIEG bit in the system control register The NMI vector number is 3 In the NMI hardware exception handling sequence the I bit in the CCR is set to 1 2 IRQ0 to IRQ2 These interrupt signals are level sensed or sensed on the falling edge of the input as selected by ISCR bits IRQ0SC to IRQ2SC These interrupts can be mas...

Page 76: ...y order see table 4 2 4 3 5 Interrupt Handling Interrupts are controlled by an interrupt controller that arbitrates between simultaneous interrupt requests commands the CPU to start the hardware interrupt exception handling sequence and furnishes the necessary vector number Figure 4 3 shows a block diagram of the interrupt controller Figure 4 3 Block Diagram of Interrupt Controller IRQ flag 0 IRQ0...

Page 77: ...n on chip RAM 1 An interrupt request is sent to the interrupt controller when an NMI interrupt occurs and when an interrupt occurs on an IRQ input line or in an on chip supporting module provided the enable bit of that interrupt is set to 1 2 The interrupt controller checks the I bit in the CCR and accepts the interrupt request if the I bit is cleared to 0 If the I bit is set to 1 only NMI request...

Page 78: ...ndling Sequence Program execution No No No Yes No Yes Yes Yes No Yes NMI I 0 IRQ0 IRQ1 ADI Reset I 1 Interrupt requested Pending Latch vector No Save PC Save CCR Read vector address Branch to software interrupt handling routine Yes 69 ...

Page 79: ...per byte PC lower byte Before interrupt is accepted After interrupt is accepted Pushed onto stack Program counter Condition code register Stack pointer PC CCR SP 1 2 The PC contains the address of the first instruction executed after return Registers must be saved and restored by word access at an even address Notes Ignored on return 70 ...

Page 80: ...routine 2 4 Instruction code Not executed 3 Instruction prefetch address Not executed 5 SP 2 6 SP 4 7 CCR 8 Address of vector table entry 9 Vector table entry address of first instruction interrupt handling routine 10 First instruction of interrupt handling routine Ø 1 2 4 7 9 10 Instruction fetch 1 Instruction prefetch address Pushed on stack Instruction is executed on return from interrupt handl...

Page 81: ...V 2 If wait states are inserted in external memory access add the number of wait states 3 1 for internal interrupts 4 3 7 Precaution Note that the following type of contention can occur in interrupt handling Contention between Interrupt Request and Disable When software clears the enable bit of an interrupt to 0 to disable the interrupt the interrupt becomes disabled after execution of the clearin...

Page 82: ...ssumed to be 0 The stack is always accessed by word access Care should be taken to keep an even value in the stack pointer general register R7 Use the PUSH and POP or MOV W Rn SP and MOV W SP Rn instructions to push and pop registers on the stack Setting the stack pointer to an odd value can cause programs to crash Figure 4 8 shows an example of damage caused when the stack pointer contains an odd...

Page 83: ...nto the stack to make a complete word When popped from the stack by an RTE instruction the CCR is loaded from the byte stored at the even address The byte stored at the odd address is ignored PCH R1 SP SP SP L PC L PC H FECD H FECF H FECC BSR instruction MOV B R1L R7 PC is improperly stored beyond top of stack H FECF set in SP PC is lost H PC Upper byte of program counter Lower byte of program cou...

Page 84: ...r If the CPU reads the data register of an output port it obtains the data held in the latch rather than the actual level of the pin Input To read data from an I O port the CPU selects input in the data direction register and reads the data register This causes the input logic level at the pin to be placed directly on the internal data bus There is no intervening input latch The data direction reg...

Page 85: ...t output P47 WAIT WAIT input General input output P46 Ø System clock General input output when DDR 0 initial state System clock output when DDR 1 P45 AS AS output General input P44 WR WR output output P43 RD RD output P42 IRQ0 General input output or external interrupt input P41 IRQ1 IRQ0 IRQ1 P40 ADTRG General input output A D converter trigger input IRQ2 ADTRG or external interrupt input IRQ2 Po...

Page 86: ...pins they have programmable MOS transistor pull ups Table 5 3 details the port 1 registers Table 5 3 Port 1 Registers Port 1 Data Direction Register P1DDR H FFB0 Mode 1 Mode 2 Mode 3 Address bus Low Input port or Input output port A7 to A0 Address bus Low A7 to A0 Name Abbreviation Read Write Initial value Address Port 1 data direction register P1DDR W H FF mode 1 H FFB0 H 00 modes 2 and 3 Port 1 ...

Page 87: ... writable register that controls the input pull up transistors in port 1 If a bit in P1DDR is cleared to 0 designating input and the corresponding bit in P1PCR is set to 1 the input pull up transistor for that bit is turned on Mode 1 In mode 1 expanded mode without on chip ROM port 1 is automatically used for address output The port 1 data direction register is unwritable All bits in P1DDR are aut...

Page 88: ...sistors that are available in modes 2 and 3 The pull up for each bit can be turned on and off individually To turn on an input pull up in mode 2 or 3 set the corresponding P1PCR bit to 1 and clear the corresponding P1DDR bit to 0 P1PCR is cleared to H 00 by a reset and in the hardware standby mode turning all input pull ups off In software standby mode the previous state is maintained Table 5 4 in...

Page 89: ...s High Input port or Input output port A15 to A8 Address bus High A15 to A8 Note Depending on the bit settings in the data direction register 0 input pin 1 address pin P1n Hardware standby Mode 3 Mode 1 or 2 RP1 Reset Reset Mode 1 Reset WP1 WP1D WP1P R R S R Q Q Q D D D P1n DR P1n DDR P1n PCR C C C RP1P Internal address bus WP1P WP1D WP1 RP1P RP1 n 0 to 7 Note Set priority Write Port 1 PCR Write P...

Page 90: ...DDR is an 8 bit register that selects the direction of each pin in port 2 A pin functions as an output pin if the corresponding bit in P2DDR is set to 1 and as an input pin if the bit is cleared to 0 Port 2 Data Register P2DR H FFB3 P2DR is an 8 bit register containing the data for pins P27 to P20 When the CPU reads P2DR for output pins it reads the value in the P2DR latch but for input pins it ob...

Page 91: ...to 1 Mode 3 In the single chip mode port 2 is a general purpose input output port Reset A reset clears P2DDR P2DR and P2PCR to all 0 placing all pins in the input state with the pull up transistors off In mode 1 when the chip comes out of reset P2DDR is set to all 1 Hardware Standby Mode All pins are placed in the high impedance state with the pull up transistors off P2DR and P2PCR are initialized...

Page 92: ... up transistor is always off On off The input pull up transistor is on if P2PCR 1 and P2DDR 0 but off otherwise Figure 5 2 shows a schematic diagram of port 2 Figure 5 2 Port 2 Schematic Diagram P2n Hardware standby Mode 3 Mode 1 or 2 RP2 Reset Reset Mode 1 Reset WP2 WP2D WP2P R R S R Q Q Q D D D P2n DR P2n DDR P2n PCR C C C RP2P Internal address bus WP2P WP2D WP2 RP2P RP2 n 0 to 7 Note Set priori...

Page 93: ...r pull ups Table 5 9 details the port 3 registers Table 5 9 Port 3 Registers Name Abbreviation Read Write Initial value Address Port 3 data direction register P3DDR W H 00 H FFB4 Port 3 data register P3DR R W H 00 H FFB6 Port 3 input pull up control P3PCR R W H 00 H FFAE register Port 3 Data Direction Register P3DDR H FFB4 P3DDR is an 8 bit register that selects the direction of each pin in port 3...

Page 94: ...rite R W R W R W R W R W R W R W R W P3PCR is an 8 bit readable writable register that controls the input pull up transistors in port 3 If a bit in P3DDR is cleared to 0 designating input and the corresponding bit in P3PCR is set to 1 the input pull up transistor for that bit is turned on Modes 1 and 2 In the expanded modes port 3 is automatically used as the data bus The values in P3DDR P3DR and ...

Page 95: ...ch bit can be turned on and off individually To turn on an input pull up in mode 3 set the corresponding P3PCR bit to 1 and clear the corresponding P3DDR bit to 0 P3PCR is cleared to H 00 by a reset and in the hardware standby mode turning all input pull ups off In software standby mode the previous state is maintained Table 5 10 indicates the states of the input pull up transistors in each operat...

Page 96: ... WP3P R R R Q Q Q D D D P3n DR P3n DDR P3n PCR C C C Internal data bus RP3 External address write Mode 1 or 2 External address read WP3P WP3D WP3 RP3P RP3 n 0 to 7 Write Port 3 PCR Write Port 3 DDR Write Port 3 Read Port 3 PCR Read Port 3 Mode 3 Mode 3 RP3P Mode 3 87 ...

Page 97: ...t output and IRQ1 input simultaneously P42 P42 input output and IRQ0 input simultaneously P43 RD output P43 input output P44 WR output P44 input output P45 AS output P45 input output P46 Ø output P46 input or Ø output P47 WAIT input P47 input output Pins of port 4 can drive a single TTL load and a 90pF capacitive load when they are used as output pins Table 5 12 details the port 4 registers Table ...

Page 98: ...ontrol signal input or output Pins P40 P41 and P42 Can be used for general purpose input or output interrupt request input or A D trigger input See table 5 11 If a pin is used for interrupt or A D trigger input its data direction bit should be cleared to 0 so that the output from P4DR will not generate an interrupt request or A D trigger signal Pins P43 P44 and P45 In modes 1 and 2 the expanded mo...

Page 99: ... input of the WAIT bus control signal It is unaffected by the values in P4DDR and P4DR In mode 3 single chip mode this pin can be used for general purpose input or output Reset In the single chip mode mode 3 a reset initializes all pins of port 4 to the general purpose input function In the expanded modes modes 1 and 2 P40 to P42 are initialized as input port pins and P43 to P47 are initialized to...

Page 100: ...state Figures 5 4 to 5 8 show schematic diagrams of port 4 Figure 5 4 Port 4 Schematic Diagram Pin P40 P40 RP4 Reset Reset WP4 WP4D R R Q Q D D P40 DR P4 0 DDR C C Internal data bus WP4D WP4 RP4 Write Port 4 DDR Write Port 4 Read Port 4 IRQ enable register IRQ2 enable IRQ2 input A D converter module ADTRG 91 ...

Page 101: ...iagram Pins P41 and P42 P4n RP4 Reset Reset WP4 WP4D R R Q Q D D P4n DR P4n DDR C C WP4D WP4 RP4 n 1 2 Write Port 4 DDR Write Port 4 Read Port 4 IRQ enable register IRQ0 enable IRQ1 enable IRQ0 input IRQ1 input Internal data bus 92 ...

Page 102: ...ns P43 P44 and P45 RP4 Reset Reset WP4 WP4D R R Q Q D D P4n DR P4n DDR C C WP4D WP4 RP4 n 3 4 5 Write Port 4 DDR Write Port 4 Read Port 4 RD output WR output AS ouput P4 n Internal data bus Hardware standby Mode 1 or 2 Mode 3 Mode 1 or 2 93 ...

Page 103: ...Figure 5 7 Port 4 Schematic Diagram Pin P46 P46 RP9 Reset WP4D R Q D P46 DDR C Internal data bus WP4D WP4 RP4 Note Set priority Write Port 4 DDR Write Port 4 Read Port 4 Hardware standby Mode 1 2 Ø S 94 ...

Page 104: ...Figure 5 8 Port 4 Schematic Diagram Pin P47 P47 RP4 Reset Reset WP4 WP4D R R Q Q D D P47 DR P47 DDR C C Internal data bus WP4D WP4 RP4 Write Port 4 DDR Write Port 4 Read Port 4 Mode 1 or 2 WAIT input 95 ...

Page 105: ...e serial communication interface are switched between input and output without regard to the values in the data direction register Pins of port 5 can drive a single TTL load and a 30pF capacitive load when they are used as output pins They can also drive a Darlington pair Table 5 14 details the port 5 registers Table 5 14 Port 5 Registers Name Abbreviation Read Write Initial value Address Port 5 d...

Page 106: ...input of serial receive data RxD When used for RxD input this pin is unaffected by P5DDR and P5DR Pin P52 This pin can be used for general purpose input or output or for serial clock input or output SCK When used for SCK input or output this pin is unaffected by P5DDR and P5DR Reset and Hardware Standby Mode A reset or entry to the hardware standby mode makes all pins of port 5 into input port pin...

Page 107: ...5 Schematic Diagram Pin P50 RP5 Reset Reset WP5 WP5D R R Q Q D D P50 DR P50 DDR C C WP5D WP5 RP5 Write Port 5 DDR Write Port 5 Read Port 5 SCI module Serial transmit enable Serial transmit data P50 Internal data bus 98 ...

Page 108: ... 5 Schematic Diagram Pin P51 P51 RP5 Reset Reset WP5 WP5D R R Q Q D D P51 DR P51 DDR C C Internal data bus WP5D WP5 RP5 Write Port 5 DDR Write Port 5 Read Port 5 SCI module Serial receive enable Serial receive data 99 ...

Page 109: ... RP5 Reset Reset WP5 WP5D R R Q Q D D P52 DR P52 DDR C C WP5D WP5 RP5 Write Port 5 DDR Write Port 5 Read Port 5 SCI module Serial clock input enable Serial clock output enble Serial clock output enable Serial clock input P52 Internal data bus 100 ...

Page 110: ...Bit Free Running Timer and section 7 8 Bit Timers for details of the timer control bits Pins of port 6 can drive a single TTL load and a 90pF capacitive load when they are used as output pins They can also drive a Darlington pair Table 5 16 details the port 6 registers Table 5 16 Port 6 Registers Name Abbreviation Read Write Initial value Address Port 6 data direction register P6DDR W H 00 H FFB9 ...

Page 111: ...2 This pin can be used for general purpose input or output and input of the FTIA input capture signal to the 16 bit free running timer FTIA input can operate simultaneously with general purpose input or output Pin P63 This pin can be used for general purpose input or output input of the FTIB input capture signal to the 16 bit free running timer and input of the timer reset signal to 8 bit timer 0 ...

Page 112: ...t timer output When 16 bit timer output is selected by the OEB bit of the 16 bit free running timer this pin is unaffected by the values in P6DDR and P6DR Pin P67 This pin can be used for general purpose input or output or output from 8 bit timer 1 When 8 bit timer output is selected by the OS bits of 8 bit timer 1 this pin is unaffected by the values in P6DDR and P6DR Reset and Hardware Standby M...

Page 113: ...gram Pin P60 P60 RP6 Reset Reset WP6 WP6D R R Q Q D D P60 DR P60 DDR C C Internal data bus WP6D WP6 RP6 Write Port 6 DDR Write Port 6 Read Port 6 8 bit timer module Counter clock input Free running timer module Counter clock input 104 ...

Page 114: ...hematic Diagram Pin P61 RP6 Reset Reset WP6 WP6D R R Q Q D D P61 DR P61 DDR C C WP6D WP6 RP6 Write Port 6 DDR Write Port 6 Read Port 6 Free running timer module Output enable Output compare output P61 Internal data bus 105 ...

Page 115: ...ort 6 Schematic Diagram Pin P62 P62 RP6 Reset Reset WP6 WP6D R R Q Q D D P62 DR P62 DDR C C Internal data bus WP6D WP6 RP6 Write Port 6 DDR Write Port 6 Read Port 6 Input capture input Free running timer module 106 ...

Page 116: ...P65 P6n RP6 Reset Reset WP6 WP6D R R Q Q D D P6n DR P6n DDR C C Internal data bus WP6D WP6 RP6 n 3 5 Write Port 6 DDR Write Port 6 Read Port 6 8 bit timer module Counter clock input Counter reset input Free running timer module Input capture input 107 ...

Page 117: ...n P64 RP6 Reset Reset WP6 WP6D R R Q Q D D P64 DR P64 DDR C C WP6D WP6 RP6 Write Port 6 DDR Write Port 6 Read Port 6 8 bit timer module Output enable 8 bit timer output P64 Internal data bus Free running timer module Input capture input 108 ...

Page 118: ... P66 RP6 Reset Reset WP6 WP6D R R Q Q D D P66 DR P66 DDR C C WP6D WP6 RP6 Write Port 6 DDR Write Port 6 Read Port 6 Free running timer module Output enable Output compare output P66 Internal data bus 8 bit timer module Counter reset input 109 ...

Page 119: ... 6 Schematic Diagram Pin P67 RP6 Reset Reset WP6 WP6D R R Q Q D D P67 DR P67 DDR C C WP6D WP6 RP6 Write Port 6 DDR Write Port 6 Read Port 6 8 bit timer module Output enable 8 bit timer output P67 Internal data bus 110 ...

Page 120: ... of port 7 Table 5 17 Port 7 Pin Functions Modes 1 to 3 Usage Pin functions I O port P70 P71 P72 P73 P74 P75 P76 P77 Analog input AN0 AN1 AN2 AN3 AN4 AN5 AN6 AN7 Table 5 18 Port 7 Register Name Abbreviation Read Write Initial value Address Port 7 data register P7DR R Undetermined H FFBE Port 7 Data Register P7DR H FFBE Note Depends on the levels of pins P77 to P70 Figure 5 19 Port 7 Schematic Diag...

Page 121: ...112 ...

Page 122: ...ree running counter can be driven by an internal clock source Ø 2 Ø 8 or Ø 32 or an external clock input enabling use as an external event counter Two independent comparators Each comparator can generate an independent waveform Four input capture channels The current count can be captured on the rising or falling edge selectable of an input signal The four input capture registers can be used separ...

Page 123: ...FTOB Overflow ICRA H L match A Compare match B Capture FRC H L TCSR FTIA FTIB FTIC FTID Control logic Module data bus TIER TCR TOCR OCIB OCIA FOVI Interrupt signals ICIA ICIB ICIC ICID FRC OCRA B ICRA B C D TCSR Free Running Counter 16 bits Output Compare Register A B 16 bits Input Capture Register A B C D 16 bits Timer Control Status Register 8 bits TIER TCR TOCR Timer Interrupt Enable Register 8...

Page 124: ...Input Trigger for capturing current count into input capture register A Input capture B FTIB Input Trigger for capturing current count into input capture register B Input capture C FTIC Input Trigger for capturing current count into input capture register C Input capture D FTID Input Trigger for capturing current count into input capture register D Initial Name Abbreviation R W value Address Timer...

Page 125: ...EMP is used when the FRC is written or read See section 6 3 CPU Interface for details The FRC is initialized to H 0000 at a reset and in the standby modes It can also be cleared by compare match A Initial Name Abbreviation R W value Address Input capture register B High ICRB H R H 00 H FF9A Input capture register B Low ICRB L R H 00 H FF9B Input capture register C High ICRC H R H 00 H FF9C Input c...

Page 126: ...ction 6 3 CPU Interface OCRA and OCRB are initialized to H FFFF at a reset and in the standby modes 6 2 3 Input Capture Registers A to D ICRA to ICRD H FF98 H FF9A H FF9C H FF9E Each input capture register is a 16 bit read only register When the rising or falling edge of the signal at an input capture pin FTIA to FTID is detected the current value of the FRC is copied to the corresponding input ca...

Page 127: ... Similarly when the BUFEB bit in TIER is set to 1 ICRD is used as a buffer register for ICRB When input capture is buffered if the two input edge bits are set to different values IEDGA IEDGC or IEDGB IEDGD then input capture is triggered on both the rising and falling edges of the FTIA or FTIB input signal If the two input edge bits are set to the same value IEDGA IEDGC or IEDGB IEDGD then input c...

Page 128: ... FTIA Because the input capture registers are 16 bit registers a temporary register TEMP is used when they are read See section 6 3 CPU Interface for details To ensure input capture the width of the input capture pulse FTIA FTIB FTIC FTID should be at least 1 5 system clock periods 1 5 Ø When triggering is enabled on both edges the input capture pulse width should be at least 2 5 system clock peri...

Page 129: ...ster TCSR is set to 1 Bit 6 Input Capture Interrupt B Enable ICIBE This bit selects whether to request input capture interrupt B ICIB when input capture flag B ICFB in the timer status control register TCSR is set to 1 Bit 5 Input Capture Interrupt C Enable ICICE This bit selects whether to request input capture interrupt C ICIC when input capture flag C ICFC in the timer status control register T...

Page 130: ...o 1 Bit 1 Timer Overflow Interrupt Enable OVIE This bit selects whether to request a free running timer overflow interrupt FOVI when the timer overflow flag OVF in the timer status control register TCSR is set to 1 Bit 5 ICICE Description 0 Input capture interrupt request C ICIC is disabled Initial value 1 Input capture interrupt request C ICIC is enabled Bit 4 ICIDE Description 0 Input capture in...

Page 131: ...BUFEA 0 ICFA indicates that the FRC value has been copied to ICRA If BUFEA 1 ICFA indicates that the old ICRA value has been moved into ICRC and the new FRC value has been copied to ICRA ICFA must be cleared by software It is set by hardware however and cannot be set by software Bit 1 OVIE Description 0 Timer overflow interrupt request FOVI is disabled Initial value 1 Timer overflow interrupt requ...

Page 132: ... cleared by software It is set by hardware however and cannot be set by software Bit 4 Input Capture Flag D ICFD This status bit is set to 1 to flag input of a rising or falling edge of FTID as selected by the IEDGD bit When BUFEB 0 this indicates capture of the FRC count in ICRD When BUFEB 1 however the FRC count is not captured so ICFD becomes simply an external interrupt flag In other words the...

Page 133: ...y hardware however and cannot be set by software Bit 4 ICFD Description 0 To clear ICFD the CPU must read ICFD after it Initial value has been set to 1 then write a 0 in this bit 1 This bit is set to 1 when an FTID input signal is received Bit 3 OCFA Description 0 To clear OCFA the CPU must read OCFA after Initial value it has been set to 1 then write a 0 in this bit 1 This bit is set to 1 when FR...

Page 134: ...A signal FTIA Bit 6 Input Edge Select B IEDGB This bit causes input capture B events to be recognized on the selected edge of the input capture B signal FTIB Bit 0 CCLRA Description 0 The FRC is not cleared Initial value 1 The FRC is cleared at compare match A Bit 7 6 5 4 3 2 1 0 IEDGA IEDGB IEDGC IEDGD BUFEA BUFEB CKS1 CKS0 Initial value 0 0 0 0 0 0 0 0 Read Write R W R W R W R W R W R W R W R W ...

Page 135: ...or one of three internal clock sources for the FRC External clock pulses are counted on the rising edge Bit 5 IEDGC Description 0 Input capture C events are recognized on the falling edge of FTIC Initial value 1 Input capture C events are recognized on the rising edge of FTIC Bit 4 IEDGD Description 0 Input capture D events are recognized on the falling edge of FTID Initial value 1 Input capture D...

Page 136: ...ows Upper byte of OCRA and upper byte of OCRB H FF94 Lower byte of OCRA and lower byte of OCRB H FF95 Bit 3 Output Enable A OEA This bit enables or disables output of the output compare A signal FTOA Bit 1 Bit 0 CKS1 CKS0 Description 0 0 Ø 2 Internal clock source Initial value 0 1 Ø 8 Internal clock source 1 0 Ø 32 Internal clock source 1 1 External clock source rising edge Bit 7 6 5 4 3 2 1 0 OCR...

Page 137: ...ytes are written or read simultaneously the access is performed using an 8 bit temporary register TEMP These registers are written and read as follows Register Write When the CPU writes to the upper byte the byte of write data is placed in TEMP Next when the CPU writes to the lower byte this byte of data is combined with the byte in TEMP and all 16 bits are written in the register simultaneously B...

Page 138: ...two consecutive byte accesses Data will not be transferred correctly if the bytes are accessed in reverse order or if only one byte is accessed Coding Examples To write the contents of general register R0 to OCRA MOV W R0 OCRA To transfer the contents of ICRA to general register R0 MOV W ICRA R0 Figure 6 4 shows the data flow when the FRC is accessed The other registers are accessed in the same wa...

Page 139: ...elected by bits CKS0 and CKS1 in the TCR Internal Clock The internal clock sources Ø 2 Ø 8 Ø 32 are created from the system clock Ø by a prescaler The FRC increments on a pulse generated from the falling edge of the prescaler output See figure 6 5 1 Upper byte read Bus interface Module data bus CPU reads data H AA TEMP H 55 FRCH H AA FRCL H 55 2 Lower byte read Bus interface Module data bus CPU re...

Page 140: ...rement timing The pulse width of the external clock signal must be at least 1 5 system clock Ø periods The counter will not increment correctly if the pulse width is shorter than 1 5 system clock periods Figure 6 6 Increment Timing for External Clock Source Figure 6 7 Minimum External Clock Pulse Width Ø Internal clock FRC clock pulse FRC N 1 N N 1 N N 1 Ø FTCI FRC FRC clock pulse Ø FTCI 131 ...

Page 141: ...h signal is generated at the last state in which the two values match just before the FRC increments to a new value Accordingly when the FRC and OCR values match the compare match signal is not generated until the next period of the clock source Figure 6 8 shows the timing of the setting of the output compare flags Figure 6 8 Setting of Output Compare Flags N N N 1 Ø FRC OCR Internal compare match...

Page 142: ...ccurs Figure 6 10 shows the timing of this operation Figure 6 10 Clearing of FRC by Compare Match A 6 4 3 Input Capture Timing 1 Input Capture Timing An internal input capture signal is generated from the rising or falling edge of the signal at the input capture pin FTIx x A B C D as selected by the corresponding IEDGx bit in TCR Figure 6 11 shows the usual input capture timing when the rising edg...

Page 143: ...RC are used in buffer mode for example if the upper byte of either ICRA or ICRC is being read when the FTIA input arrives the internal input capture signal is delayed by one state Figure 6 13 shows the timing for this case The case of ICRB and ICRD is similar Figure 6 13 Input Capture Timing 1 State Delay Buffer Mode Ø Input at FTI pin Internal input capture signal Read cycle CPU reads upper byte ...

Page 144: ...edges of FTIA Figure 6 14 Buffered Input Capture with Both Edges Selected In this mode FTIC does not cause the FRC contents to be copied to ICRC However input capture flag C still sets on the edge of FTIC selected by IEDGC and if the interrupt enable bit ICICE is set a CPU interrupt is requested The situation when ICRB and ICRD are used in buffer mode is similar N N 1 n n 1 n M M m N n n M Ø FTIA ...

Page 145: ...on Figure 6 15 Setting of Input Capture Flag 6 4 4 Setting of FRC Overflow Flag OVF The FRC overflow flag OVF is set to 1 when the FRC overflows changes from H FFFF to H 0000 Figure 6 16 shows the timing of this operation Figure 6 16 Setting of Overflow Flag OVF OVF Ø FRC Internal overflow signal H FFFF H 0000 Ø Internal input capture signal ICFA B C D FRC ICRA B C D N N 136 ...

Page 146: ...nerate two square wave outputs with a 50 duty cycle and arbitrary phase relationship The programming is as follows 1 The CCLRA bit in the TCSR is set to 1 2 Each time a compare match interrupt occurs software inverts the corresponding output level bit in TOCR OLVLA or OLVLB Figure 6 17 Square Wave Output Example Interrupt Description Priority ICIA Requested when ICFA and ICIAE are set High ICIB Re...

Page 147: ...r clear signal is generated during the T3 state of a write cycle to the lower byte of the free running counter the clear signal takes priority and the write is not performed Figure 6 18 shows this type of contention Figure 6 18 FRC Write Clear Contention Write cycle CPU write to lower byte of FRC FRC address N H 0000 T1 T2 T3 Ø Internal address bus Internal write signal FRC clear signal FRC 138 ...

Page 148: ...lower byte of the free running counter the write takes priority and the FRC is not incremented Figure 6 19 shows this type of contention Figure 6 19 FRC Write Increment Contention Write cycle CPU write to lower byte of FRC FRC address Ø Internal address bus Internal write signal FRC clock pulse FRC N M T T T Write data 1 2 3 139 ...

Page 149: ... takes priority and the compare match signal is inhibited Figure 6 20 shows this type of contention Figure 6 20 Contention between OCR Write and Compare Match Write cycle CPU write to lower byte of OCRA or OCRB OCR address N N 1 N M Inhibited Write data Ø Internal address bus Internal write signal Compare match A or B signal OCRA or OCRB FRC T1 T T 2 3 140 ...

Page 150: ... source is Low as in case No 3 in table 6 5 the changeover generates a falling edge that triggers the FRC increment clock pulse Switching between an internal and external clock source can also cause the FRC to increment Table 6 5 Effect of Changing Internal Clock Sources No Description Timing chart Low Low CKS1 and CKS0 are 1 rewritten while both clock sources are Low Low High CKS1 and CKS0 are 2 ...

Page 151: ...Description Timing chart High Low CKS1 and CKS0 are 3 rewritten while old clock source is High and new clock source is Low High High CKS1 and CKS0 are 4 rewritten while both clock sources are High Old clock source New clock source FRC clock pulse FRC N N 1 CKS rewrite N 2 Old clock source New clock source FRC clock pulse FRC N N 1 N 2 CKS rewrite 142 ...

Page 152: ... counters can be driven by one of six internal clock signals or an external clock input enabling use as an external event counter Selection of three ways to clear the counters The counters can be cleared on compare match A or B or by an external reset signal Timer output controlled by two time constants The timer output signal in each channel is controlled by two independent time constants enablin...

Page 153: ...ect TCORA Comparator A TCNT Comparator B TCORB TCSR TCR Module data bus Bus interface Internal data bus CMIA CMIB OVI Interrupt signals TCR TCSR TCORA TCORB TCNT Timer Control Register 8 bits Timer Control Status Register 8 bits Time Constant Register A 8 bits Time Constant Register B 8 bits Timer Counter Compare match A Abbreviation Name TMR0 TMR1 I O Function Timer output TMO0 TMO1 Output Output...

Page 154: ... control register TCR The CPU can always read or write the timer counter The timer counter can be cleared by an external reset input or by an internal compare match signal generated at a compare match event Clock clear bits 1 and 0 CCLR1 and CCLR0 of the timer control register select the method of clearing When a timer counter overflows from H FF to H 00 the overflow flag OVF in the timer control ...

Page 155: ...y modes Compare match is not detected during the T3 state of a write cycle to TCORA or TCORB See item 3 in section 7 6 Application Notes 7 2 3 Timer Control Register TCR H FFC8 TMR0 H FFD0 TMR1 Each TCR is an 8 bit readable writable register that selects the clock source and the time at which the timer counter is cleared and enables interrupts The TCRs are intialized to H 00 at a reset and in the ...

Page 156: ...d Bit 5 OVIE Description 0 The timer overflow interrupt request OVI is disabled Initial value 1 The timer overflow interrupt request OVI is enabled Bit 4 Bit 3 CCLR1 CCLR0 Description 0 0 Not cleared Initial value 0 1 Cleared on compare match A 1 0 Cleared on compare match B 1 1 Cleared on rising edge of external reset input signal 147 Bit 5 Timer Overflow Interrupt Enable OVIE This bit selects wh...

Page 157: ... Ø 64 internal clock counted on falling edge 0 1 0 1 Ø 32 internal clock counted on falling edge 0 1 1 0 Ø 1024 internal clock counted on falling edge 0 1 1 1 Ø 256 internal clock counted on falling edge 1 0 0 No clock source timer stopped 1 0 1 External clock source counted on rising edge 1 1 0 External clock source counted on falling edge 1 1 1 External clock source counted on both rising and fa...

Page 158: ...timer count Bit 6 Compare Match Flag A CMFA This status flag is set to 1 when the timer count matches the time constant set in TCORA CMFA must be cleared by software It is set by hardware however and cannot be set by software Bit 7 6 5 4 3 2 1 0 CMFB CMFA OVF OS3 OS2 OS1 OS0 Initial value 0 0 0 1 0 0 0 0 Read Write R W R W R W R W R W R W R W Bit 7 CMFB Description 0 To clear CMFB the CPU must rea...

Page 159: ...on 7 6 Application Notes After a reset the timer output is 0 until the first compare match event When all four output select bits are cleared to 0 the timer output signal is disabled Bit 5 OVF Description 0 To clear OVF the CPU must read OVF after Initial value it has been set to 1 then write a 0 in this bit 1 This bit is set to 1 when TCNT changes from H FF to H 00 Bit 3 Bit 2 OS3 OS2 Description...

Page 160: ...ters The STCR is initialized to H F8 at a reset Bits 7 to 3 Reserved These bits cannot be modified and are always read as 1 Bit 2 Multiprocessor Enable MPE Controls the operating mode of the serial communication interface For details see section 8 Serial Communication Interface Bits 1 and 0 Internal Clock Source Select 1 and 0 ICKS1 and ICKS0 These bits and bits CKS2 to CKS0 in the TCR select cloc...

Page 161: ...ect one of the six internal clocks Figure 7 2 Count Timing for Internal Clock Input External Clock If external clock input TMCI is selected the timer counter can increment on the rising edge the falling edge or both edges of the external clock signal Figure 7 3 shows incrementation on both edges of the external clock signal The external clock pulse width must be at least 1 5 system clock periods f...

Page 162: ...by an internal compare match signal generated when the timer count matches the time constant in TCNT or TCOR The compare match signal is generated at the last state in which the match is true just before the timer counter increments to a new value External clock source TCNT clock pulse TCNT N N 1 Ø N 1 Ø TMCI Ø TMCI Minimum TMCI Pulse Width Single Edge Incrementation Minimum TMCI Pulse Width Doubl...

Page 163: ...s 2 Output Timing When a compare match event occurs the timer output TMO0 or TMO1 changes as specified by the output select bits OS3 to OS0 in the TCSR Depending on these bits the output can remain the same change to 0 change to 1 or toggle Figure 7 6 shows the timing when the output is set to toggle on compare match A Figure 7 6 Timing of Timer Output TCNT TCOR Internal compare match signal CMF N...

Page 164: ...ar 7 3 3 External Reset of TCNT When the CCLR1 and CCLR0 bits in the TCR are both set to 1 the timer counter is cleared on the rising edge of an external reset input Figure 7 8 shows the timing of this operation The timer reset pulse width must be at least 1 5 system clock periods Figure 7 8 Timing of External Reset N H 00 Internal compare match signal TCNT ø Ø External reset input TMRI Internal c...

Page 165: ... of TCSR Overflow Flag OVF The overflow flag OVF is set to 1 when the timer count overflows changes from H FF to H 00 Figure 7 9 shows the timing of this operation H 00 TCNT Internal overflow signal OVF H FF ø Ø 156 ...

Page 166: ...ontrol bits are set as follows 1 In the TCR CCLR1 is cleared to 0 and CCLR0 is set to 1 so that the timer counter is cleared when its value matches the constant in TCORA 2 In the TCSR bits OS3 to OS0 are set to 0110 causing the output to change to 1 on compare match A and to 0 on compare match B With these settings the 8 bit timer provides output of pulses at a rate determined by TCORA with a puls...

Page 167: ...ternal counter clear signal is generated during the T3 state of a write cycle to the timer counter the clear signal takes priority and the write is not performed Figure 7 11 shows this type of contention Figure 7 11 TCNT Write Clear Contention Ø Internal Address bus Internal write signal Counter clear signal TCNT N H 00 TCNT address Write cycle CPU writes to TCNT T1 T2 T3 158 ...

Page 168: ...type of contention Figure 7 12 TCNT Write Increment Contention 3 Contention between TCOR Write and Compare Match If a compare match occurs during the T3 state of a write cycle to TCORA or TCORB the write takes precedence and the compare match signal is inhibited Figure 7 13 shows this type of contention Ø Internal Address bus Internal write signal TCNT clock pulse TCNT N M TCNT address Write cycle...

Page 169: ...ly any conflict between the output selections for compare match A and B is resolved by following the priority order in table 7 4 Table 7 4 Priority of Timer Output Ø Internal address bus Internal write signal TCNT N M TCOR address Write cycle CPU writes to TCORA or TCORB N N 1 TCORAor TCORB Compare match A or B signal T1 Inhibited TCOR write data T2 T3 Output selection Priority Toggle High 1 Outpu...

Page 170: ...TCNT clock pulse and increments the timer counter Switching between an internal and external clock source can also cause the timer counter to increment Table 7 5 Effect of Changing Internal Clock Sources Notes 1 Including a transition from Low to the stopped state CKS1 0 CKS0 0 or a transition from the stopped state to Low 2 Including a transition from the stopped state to High No Description Timi...

Page 171: ...crements the TCNT No Description Timing chart High Low 1 Clock select bits are 3 rewritten while old clock source is High and new clock source is Low High High Clock select bits are 4 rewritten while both clock sources are High Old clock source New clock source TCNT clock pulse TCNT CKS rewrite N N 1 N 2 3 2 N 1 N Old clock source New clock source TCNT clock pulse TCNT CKS rewrite N 2 162 ...

Page 172: ...Multiprocessor bit 1 or 0 Error detection Parity overrun and framing errors Break detection When a framing error occurs the break condition can be detected by reading the level of the RxD line directly Synchronous mode The SCI can communicate with chips able to perform clocked synchronous data transfer Data length 8 bits Error detection Overrun errors Full duplex communication The transmitting and...

Page 173: ...TSR Ø Ø 4 Ø 16 Ø 64 RxD TxD TXI RXI ERI Interrupt signals External clock source Internal clock RDR RSR SCK BRR Communi cation control SSR SCR SMR Baud rate generator RSR RDR TSR TDR SMR SCR SSR BRR Receive Shift Register 8 bits Receive Data Register 8 bits Transmit Shift Register 8 bits Transmit Data Register 8 bits Serial Mode Register 8 bits Serial Control Register 8 bits Serial Status Register ...

Page 174: ...synchronous or asynchronous data format and bit rate and control the transmit and receive sections Table 8 2 SCI Registers Name Abbr R W Value Address Receive shift register RSR Receive data register RDR R H 00 H FFDD Transmit shift register TSR Transmit data register TDR R W H FF H FFDB Serial mode register SMR R W H 00 H FFD8 Serial control register SCR R W H 00 H FFDA Serial status register SSR...

Page 175: ...d from the RSR to the RDR enabling the RSR to receive the next character This double buffering allows the SCI to receive data continuously The CPU can read but not write the RDR The RDR is initialized to H 00 at a reset and in the standby modes 8 2 3 Transmit Shift Register TSR Bit 7 6 5 4 3 2 1 0 Read Write The TSR holds the character currently being transmitted When transmission of this characte...

Page 176: ...dby modes 8 2 5 Serial Mode Register SMR H FFD8 Bit 7 6 5 4 3 2 1 0 C A CHR PE O E STOP MP CKS1 CKS0 Initial value 0 0 0 0 0 0 0 0 Read Write R W R W R W R W R W R W R W R W The SMR is an 8 bit readable writable register that controls the communication format and selects the clock rate for the internal clock source It is initialized to H 00 at a reset and in the standby modes For further informati...

Page 177: ...ultiprocessor format is used Bit 5 PE Description 0 Transmit No parity bit is added Initial value Receive Parity is not checked 1 Transmit A parity bit is added Receive Parity is checked Bit 4 Parity Mode O E In asynchronous mode when parity is enabled PE 1 this bit selects even or odd parity Even parity means that a parity bit is added to the data bits for each character to make the total number ...

Page 178: ...ected the parity settings of the parity enable bit PE and parity mode bit O E are ignored The MP bit is ignored in synchronous communication The MP bit is valid only when the MPE bit in the serial timer control register STCR is set to 1 When the MPE bit is cleared to 0 the multiprocessor communication function is disabled regardless of the setting of the MP bit Bit 2 MP Description 0 Multiprocesso...

Page 179: ...SR is set to 1 Bit 7 TIE Description 0 The TDR empty interrupt request TXI is disabled Initial value 1 The TDR empty interrupt request TXI is enabled Bit 6 Receive Interrupt Enable RIE This bit enables or disables the receive end interrupt RxI requested when the receive data register full RDRF bit in the serial status register SSR is set to 1 It also enables or disables the receive error interrupt...

Page 180: ... can be used for general purpose I O 1 The transmit function is enabled The TxD pin is used for output Bit 4 Receive Enable RE This bit enables or disables the receive function When the receive function is enabled the RxD pin is automatically used for input When the receive function is disabled the RxD pin is available as a general purpose I O port Bit 4 RE Description 0 The receive function is di...

Page 181: ...e data is 0 the receive end interrupt RxI and receive error interrupt ERI are disabled the receive data are not transferred from the RSR to the RDR and the RDRF FER PER and ORER bits in the serial status register SSR are not set If the multiprocessor bit is 1 however the MPB bit in the SSR is set to 1 the MPIE bit is cleared to 0 the FER PER and ORER bits can be set and the receive end and receive...

Page 182: ...Bit 1 CKE1 Description 0 Internal clock source Initial value When C A 1 the serial clock signal is output at the SCK pin When C A 0 output depends on the CKE0 bit 1 External clock source The SCK pin is used for input Bit 0 Clock Enable 0 CKE0 When an internal clock source is used in asynchronous mode this bit enables or disables serial clock output at the SCK pin This bit is ignored when the exter...

Page 183: ...e TSR and the next character can safely be written in the TDR Bit 7 TDRE Description 0 To clear TDRE the CPU must read TDRE after it has been set to 1 then write a 0 in this bit 1 This bit is set to 1 at the following times Initial value 1 When TDR contents are transferred to the TSR 2 When the TE bit in the SCR is cleared to 0 Bit 6 Receive Data Register Full RDRF This bit indicates when one char...

Page 184: ...clear FER the CPU must read FER after Initial value it has been set to 1 then write a 0 in this bit 1 This bit is set to 1 if a framing error occurs stop bit 0 Bit 3 Parity Error PER This bit indicates a parity error during data reception in the asynchronous mode when a communication format with parity bits is used This bit has no meaning in the synchronous mode or when a communication format with...

Page 185: ...e value of the multiprocessor bit in data received in a multiprocessor format in asynchronous communication mode In synchronous mode when a multiprocessor format is not used or if the RE bit is cleared to 0 when a multiprocessor format is used the MPB bit retains its previous value MPB can be read but not written Bit 1 MPB Description 0 Multiprocessor bit 0 in receive data Initial value 1 Multipro...

Page 186: ...how examples of BRR N and CKS n settings for commonly used bit rates Table 8 3 Examples of BRR Settings in Asynchronous Mode 1 XTAL frequency MHz 2 2 4576 4 4 194304 Bit Error Error Error Error rate n N n N n N n N 110 1 70 0 03 1 86 0 31 1 141 0 03 1 148 0 04 150 0 207 0 16 0 255 0 1 103 0 16 1 108 0 21 300 0 103 0 16 0 127 0 0 207 0 16 0 217 0 21 600 0 51 0 16 0 63 0 0 103 0 16 0 108 0 21 1200 0...

Page 187: ...0 0 9 2 34 0 11 0 0 12 0 16 19200 0 3 0 0 4 2 34 0 5 0 31250 0 2 0 0 3 0 38400 0 1 0 0 2 0 Table 8 3 Examples of BRR Settings in Asynchronous Mode 3 XTAL frequency MHz 9 8304 10 12 12 288 Bit Error Error Error Error rate n N n N n N n N 110 2 86 0 31 2 88 0 25 2 106 0 44 2 108 0 08 150 1 255 0 2 64 0 16 2 77 0 2 79 0 300 1 127 0 1 129 0 16 1 155 0 1 159 0 600 0 255 0 1 64 0 16 1 77 0 1 79 0 1200 0...

Page 188: ... 207 0 16 0 255 0 1 64 0 16 2400 0 95 0 0 103 0 16 0 127 0 0 129 0 16 4800 0 47 0 0 51 0 16 0 63 0 0 64 0 16 9600 0 23 0 0 25 0 16 0 31 0 0 32 1 36 19200 0 11 0 0 12 0 16 0 15 0 0 15 1 73 31250 0 7 0 0 9 1 70 0 9 0 38400 0 5 0 0 7 0 0 7 1 73 Note If possible the error should be within 1 B OSC 106 64 22n N 1 N BRR value 0 N 255 OSC Crystal oscillator frequency in MHz B Bit rate bits second n Intern...

Page 189: ... 0 9 0 19 0 39 0 49 0 79 0 99 50k 0 4 0 9 0 19 0 24 0 39 0 49 100k 0 4 0 9 0 19 0 24 250k 0 0 0 1 0 3 0 4 0 7 0 9 500k 0 0 0 1 0 3 0 4 1M 0 0 0 1 2 5M 0 0 Notes Blank No setting is available A setting is available but the bit rate is inaccurate Continuous transfer is not possible B OSC 106 8 22n N 1 N BRR value 0 N 255 OSC Crystal oscillator frequency in MHz B Bit rate bits second n Internal clock...

Page 190: ...fied and are always read as 1 Bit 2 Multiprocessor Enable MPE Enables or disables the SCI s multiprocessor communication function Bit 2 MPE Description 0 The multiprocessor communication function is disabled Initial value regardless of the setting of the MP bit in SMR 1 The multiprocessor communication function is enabled The multi processor format can be selected by setting the MP bit in SMR to 1...

Page 191: ...FER parity errors PER and overrun errors ORER can be detected in receive data and the line break condition can be detected An internal or external clock source can be selected for the serial clock When an internal clock source is selected the SCI is clocked by the on chip baud rate generator and can output a clock signal at the bit rate frequency When the external clock source is selected the on c...

Page 192: ...ent 1 bit 1 2 bits 0 1 0 Asynchronous mode 8 bits Present None 1 bit 1 multiprocessor 2 bits 1 0 format 7 bits 1 bit 1 2 bits 1 Synchronous mode 8 bits None None Table 8 6 SCI Clock Source Selection SMR SCR Bit 7 Bit 1 Bit 0 Serial transmit receive clock C A CKE1 CKE0 Mode Clock source SCK pin function 0 0 0 Async Internal Input output port not used by SCI 1 Serial clock output at bit rate 1 0 Ext...

Page 193: ...it transmitted or received is the start bit Low It is followed by the data bits in which the least significant bit LSB comes first The data bits are followed by the parity or multiprocessor bit if present then the stop bit or bits High confirming the end of the frame In receiving the SCI synchronizes on the falling edge of the start bit and samples each bit at the center of the bit at the 8th cycl...

Page 194: ...sired bit rate If the internal clock provided by the on chip baud rate generator is selected and the SCK pin is used for clock output the output clock frequency is equal to the bit rate and the clock pulse rises at the center of the transmit data bits Figure 8 3 shows the phase relationship between the output clock and transmit data CHR 0 0 0 0 1 1 1 1 0 0 1 1 PE 0 0 1 1 0 0 1 1 MP 0 0 0 0 0 0 0 0...

Page 195: ...e or format always clear the TE and RE bits to 0 before following the procedure given below Clearing TE to 0 sets TDRE to 1 and initializes the transmit shift register TSR Clearing RE to 0 however does not initialize the RDRF PER FER and ORER flags and receive data register RDR which retain their previous contents When an external clock is used the clock should not be stopped during initialization...

Page 196: ...put is selected in asynchronous mode clock output starts immediately after the setting is made in SCR 4 Wait for at least the interval required to transmit or receive one bit then set TE or RE in the serial control register SCR Setting TE or RE enables the SCI to use the TxD or RxD pin Also set the RIE TIE TEIE and MPIE bits as necessary to enable interrupts The initial states are the mark transmi...

Page 197: ...can be reported by a TEI interrupt To output a break signal at the end of serial transmission set the DDR bit to 1 and clear the DR bit to 0 DDR and DR are I O port registers then clear TE to 0 in SCR If using multiprocessor format select MPBT value in SSR Clear TDRE bit to 0 in SSR Read TEND bit in SSR TEND 1 No Yes Output break signal No Yes Clear TE bit in SCR to 0 4 SCI status check and transm...

Page 198: ...it data seven or eight bits are output LSB first c Parity bit or multiprocessor bit one parity bit even or odd parity or one multiprocessor bit is output Formats in which neither a parity bit nor a multiprocessor bit is output can also be selected d Stop bit one or two 1 bits stop bits are output e Mark state output of 1 bits continues until the start bit of the next transmit data 3 The SCI checks...

Page 199: ...Transmit Operation 8 Bit Data with Parity and One Stop Bit 1 Start bit 0 D0 D1 D7 0 1 Stop bit 1 Data Parity bit Start bit 0 D0 D1 D7 0 1 Stop bit 1 Data Parity bit 1 Mark idle state TDRE TEND TXI request TXI interrupt handler writes data in TDR and clears TDRE to 0 TXI request 1 frame TEI request 190 ...

Page 200: ... read the serial status register SSR check that RDRF is set to 1 then read receive data from the receive data register RDR and clear RDRF to 0 Transition of the RDRF bit from 0 to 1 can be reported by an RXI interrupt 4 Receive error handling and break detection if a receive error occurs read the ORER PER and FER bits in SSR to identify the error After executing the necessary error handling clear ...

Page 201: ...nly the first stop bit is checked c Status check RDRF must be 0 so that receive data can be loaded from RSR into RDR If these checks all pass the SCI sets RDRF to 1 and stores the received data in RDR If one of the checks fails receive error the SCI operates as indicated in table 8 8 Note When a receive error flag is set further receiving is disabled The RDRF bit is not set to 1 Be sure to clear t...

Page 202: ... error FER Stop bit is 0 Receive data loaded from RSR into RDR Parity error PER Parity of receive data differs Receive data loaded from RSR from even odd parity setting into RDR in SMR Figure 8 8 Example of SCI Receive Operation 8 Bit Data with Parity and One Stop Bit 1 Start bit 0 D0 D1 D7 0 1 Stop bit 1 Data Parity bit Start bit 0 D0 D1 D7 0 1 Stop bit 0 Data Parity bit 1 Mark idle state RDRF FE...

Page 203: ... transmit data with the multiprocessor bit cleared to 0 Receiving processors skip incoming data until they receive data with the multiprocessor bit set to 1 After receiving data with the multiprocessor bit set to 1 the receiving processor with an ID matching the received data continues to receive further incoming data Multiple processors can send and receive data in this way Four formats are avail...

Page 204: ... 1 3 SCI status check and ID check read the serial status register SSR check that RDRF is set to 1 then read receive data from the receive data register RDR and compare with the processor s own ID Transition of the RDRF bit from 0 to 1 can be reported by an RXI interrupt If the ID does not match the receive data set MPIE to 1 again and clear RDRF to 0 If the ID matches the receive data clear RDRF ...

Page 205: ...quest MPIE 0 RXI handler reads RDR data and clears RDRF to 0 Not own ID so MPIE is set to 1 again No RXI request RDR not updated Multiprocessor interrupt a Own ID does not match data 1 Start bit 0 D0 D1 D7 1 Stop bit 1 Data ID2 MPB Start bit 0 D0 D1 D7 0 Stop bit 1 Data Data2 MPB 1 Mark idle state MPIE RDRF RDR value ID2 RXI request MPIE 0 RXI handler reads RDR data and clears RDRF to 0 Own ID so ...

Page 206: ...t in clocked synchronous serial communication Figure 8 12 Data Format in Clocked Synchronous Communication In clocked synchronous serial communication each data bit is sent on the communication line from one falling edge of the serial clock to the next Data are received in synchronization with the rising edge of the serial clock In each character the serial data bits are transmitted in order from ...

Page 207: ... an internal clock it outputs the clock signal at the SCK pin Eight clock pulses are output per transmitted or received character When the SCI is not transmitting or receiving the clock signal remains at the high level 2 Transmitting and Receiving Data SCI Initialization The SCI must be initialized in the same way as in asynchronous mode See figure 8 4 When switching from asynchronous mode to cloc...

Page 208: ... read the TDRE bit to check whether it is safe to write if TDRE 1 write data in TDR then clear TDRE to 0 To end serial transmission end of transmission can be confirmed by checking transition of the TEND bit from 0 to 1 This can be reported by a TEI interrupt Read TEND bit in SSR TEND 1 No Yes SCI status check and transmit data write read the serial status register SSR check that the TDRE bit is 1...

Page 209: ...tputs eight serial clock pulses triggered by the clearing of the TDRE bit to 0 If an external clock source is selected the SCI outputs data in synchronization with the input clock Data are output from the TxD pin in order from LSB bit 0 to MSB bit 7 3 The SCI checks the TDRE bit when it outputs the MSB bit 7 If TDRE is 0 the SCI loads data from TDR into TSR then begins serial transmission of the n...

Page 210: ...nsmit operation Figure 8 14 Example of SCI Transmit Operation Serial clock Data Bit 0 Bit 1 Bit 7 Bit 0 Bit 1 Bit 6 Bit 7 TXI request TDRE TEND TXI interrupt handler writes data in TDR and clears TDRE to 0 TXI request TEI request 1 frame 201 ...

Page 211: ...F to 0 before the MSB bit 7 of the current frame is received 4 Receive error handling if a receive error occurs read the ORER bit in SSR then after executing the necessary error handling clear ORER to 0 Neither transmitting nor receiving can resume while ORER remains set to 1 When clock output mode is selected receiving can be halted temporarily by receiving one dummy byte and causing an overrun e...

Page 212: ...DR If this check passes the SCI sets RDRF to 1 and stores the received data in RDR If the check does not pass receive error the SCI operates as indicated in table 8 8 Note Both transmitting and receiving are disabled while a receive error flag is set The RDRF bit is not set to 1 Be sure to clear the error flag 3 After setting RDRF to 1 if the RIE bit receive end interrupt enable is set to 1 in SCR...

Page 213: ...peration Figure 8 16 Example of SCI Receive Operation Serial clock Data Bit 0 Bit 1 Bit 7 Bit 0 Bit 1 Bit 6 Bit 7 RXI request RDRF ORER RXI interrupt handler reads data in RDR and clears RDRF to 0 RXI request Overrun error ERI request 1 frame 204 ...

Page 214: ... read RDR and clear RDRF to 0 before the MSB bit 7 of the current frame is received Also read the TDRE bit and check that it is set to 1 indicating that it is safe to write then write data in TDR and clear TDRE to 0 before the MSB bit 7 of the current frame is transmitted 2 SCI status check and transmit data write read the serial status register SSR check that the TDRE bit is 1 then write transmit...

Page 215: ...t the SCI has stopped transmitting data Table 8 9 SCI Interrupt Sources Interrupt Description Priority ERI Receive error interrupt ORER FER or PER High RXI Receive end interrupt RDRF TXI TDR empty interrupt TDRE TEI TSR empty interrupt TEND Low 8 5 Application Notes Application programmers should note the following features of the SCI 1 TDR Write The TDRE bit in the SSR is simply a flag that indic...

Page 216: ...he value H 00 is transferred from the RSR to the RDR Software can detect the line break state as a framing error accompanied by H 00 data in the RDR The SCI continues to receive data so if the FER bit is cleared to 0 another framing error will occur 4 Sampling Timing and Receive Margin in Asynchronous Mode The serial clock used by the SCI in asynchronous mode runs at 16 times the baud rate The fal...

Page 217: ...ctor of clock ratio of High pulse width to Low width 0 5 to 1 0 L Frame length 9 to 12 F Absolute clock frequency deviation When D 0 5 and F 0 M 0 5 1 2 16 100 46 875 2 1 2 4 0 5 6 7 8 9 3 2 1 2 3 4 5 6 7 8 9 1 1112 131415 16 10 1314 1516 12 10 11 3 4 5 Basic clock Sync sampling Data sampling D0 D1 Receive data Start bit 7 5 pulses 7 5 pulses 208 ...

Page 218: ...nalog input channels Rapid conversion Conversion time is 12 2µs per channel minimum with a 10MHz system clock External triggering can be selected Single and scan modes Single mode A D conversion is performed once Scan mode A D conversion is performed in a repeated cycle on one to four channels Sample and hold function Four 8 bit data registers These registers store A D conversion results for up to...

Page 219: ...C R Analog multi plexer Comparator Sample and hold circuit Interrupt signal Ø 8 Ø 16 Bus interface ADTRG ADI 8 Bit D A Control circuit AN0 AN2 AN1 AN3 AN4 AN5 AN6 AN7 AVCC AVSS ADCR A D Control Register 8 bits ADCSR A D Control Status Register 8 bits ADDRA A D Data Register A 8 bits ADDRB A D Data Register B 8 bits ADDRC A D Data Register C 8 bits ADDRD A D Data Register D 8 bits 210 ...

Page 220: ...alog input 2 AN2 Input Analog input 3 AN3 Input Analog input 4 AN4 Input Analog input 5 AN5 Input Analog input pins group 1 Analog input 6 AN6 Input Analog input 7 AN7 Input A D external trigger ADTRG Input External trigger for starting A D conversion 9 1 4 Register Configuration Table 9 2 lists the registers of the A D converter module Table 9 2 A D Registers Name Abbreviation R W Initial value A...

Page 221: ...ters are initialized to H 00 at a reset and in the standby modes Table 9 3 Assignment of Data Registers to Analog Input Channels Analog input channel Group 0 Group 1 A D data register AN0 AN4 ADDRA AN1 AN5 ADDRB AN2 AN6 ADDRC AN3 AN7 ADDRD 9 2 2 A D Control Status Register ADCSR H FFE8 Bit 7 6 5 4 3 2 1 0 ADF ADIE ADST SCAN CKS CH2 CH1 CH0 Initial value 0 0 0 0 0 0 0 0 Read Write R W R W R W R W R...

Page 222: ...cts whether to request an A D interrupt ADI when A D conversion is completed Bit 6 ADIE Description 0 The A D interrupt request ADI is disabled Initial value 1 The A D interrupt request ADI is enabled Bit 5 A D Start ADST The A D converter operates while this bit is set to 1 This bit can be set to 1 by the external trigger signal ADTRG Bit 5 ADST Description 0 A D conversion is halted Initial valu...

Page 223: ...y when the ADST bit is cleared to 0 Bit 3 CKS Description 0 Conversion time 242 states max Initial value 1 Conversion time 122 states max Bits 2 to 0 Channel Select 2 to 0 CH2 to CH0 These bits and the SCAN bit combine to select one or more analog input channels The channel selection should be changed only when the ADST bit is cleared to 0 Group select Channel select Selected channels CH2 CH1 CH0 ...

Page 224: ...odes Bit 7 Trigger Enable TRGE This bit enables the ADTRG A D external trigger signal to set the ADST bit and start A D conversion Bit 7 TRGE Description 0 A D external trigger is disabled ADTRG does not set Initial value the ADST bit 1 A D external trigger is enabled ADTRG sets the ADST bit The ADST bit can also be set by software Bits 6 to 1 Reserved These bits cannot be modified and are always ...

Page 225: ...he ADST bit is automatically cleared to 0 When the conversion is completed the ADF bit is set to 1 If the interrupt enable bit ADIE is also set to 1 an A D conversion end interrupt ADI is requested so that the converted data can be processed by an interrupt handling routine The ADF bit is cleared when software reads the A D control status register ADCSR then writes a 0 in this bit Before selecting...

Page 226: ...Select mode and channel and set ADST to 1 Value set in ADCSR ADF ADIE ADST SCAN CKS CH2 CH1 CH0 0 1 1 0 0 0 0 1 2 The A D converter converts the voltage level at the AN1 input pin to a digital value At the end of the conversion process the A D converter transfers the result to register ADDRB sets the ADF bit to 1 clears the ADST bit to 0 and halts 3 ADF 1 and ADIE 1 so an A D interrupt is requeste...

Page 227: ...g Waiting Waiting Set Clear A D conversion starts Set Read result Read result A D conversion result A D conversion result Set Clear ADST ADF Channel 0 AN 0 Channel 1 AN 1 Channel 2 AN 2 Channel 3 AN 3 ADDRA ADDRB ADDRC ADDRD Interrupt ADI ADIE Figure 9 2 A D Operation in Single Mode when Channel 1 is Selected 218 ...

Page 228: ... clear the ADST bit to 0 to make sure the A D converter is stopped Changing the mode clock or channel selection while A D conversion is in progress can lead to conversion errors A D conversion begins from the first selected channel when the ADST bit is set to 1 again The same instruction can be used to alter the mode and channel selection and set ADST to 1 The following example explains the A D co...

Page 229: ...N2 have been converted the AD converter sets the ADF bit to 1 If the ADIE bit is set to 1 an A D interrupt ADI is requested Then the A D converter begins converting AN0 again 5 Steps 2 to 4 are repeated cyclically as long as the ADST bit remains set to 1 To stop the A D converter software must clear the ADST bit to 0 Regardless of which channel is being converted when the ADST bit is cleared to 0 ...

Page 230: ...Waiting Waiting A D conver sion Waiting A D conver sion Waiting Waiting A D conver sion Waiting Waiting Transfer A D conver sion result A D conversion result A D conversion result A D conversion result 1 indicates execution of a software instruction Data undergoing conversion when ADST bit is cleared are ignored Notes 1 1 2 1 2 Figure 9 3 A D Operation in Scan Mode when Channels 0 to 2 are Selecte...

Page 231: ...cludes tD and tSPL The purpose of tD is to synchronize the ADCSR write time with the A D conversion process so the length of tD is variable The total conversion time therefore varies within the minimum to maximum ranges indicated in table 9 4 a and b In the scan mode the ranges given in table 9 4 b apply to the first conversion The length of the second and subsequent conversion processes is fixed ...

Page 232: ...31 Total A D conversion time tCONV 259 274 131 138 Note Values in the tables above are numbers of states 9 3 4 External Trigger Input Timing A D conversion can be started by external trigger input at the ADTRG pin This input is enabled or disabled by the TRGE bit in the A D control register ADCR If the TRGE bit is set to 1 when a falling edge of ADTRG is detected the ADST bit is set to 1 and A D c...

Page 233: ... A D conversion module generates an A D end interrupt request ADI at the end of A D conversion The ADI interrupt request can be enabled or disabled by the ADIE bit in the A D control status register ADCSR Ø ADTRG Internal trigger signal ADST A D conversion 224 ...

Page 234: ... FB80 to H FF7F in the H8 329 and H8 328 addresses H FD80 to H FF7F in the H8 327 and addresses H FE80 to H FF7F in the H8 326 The RAME bit in the system control register SYSCR can enable or disable the on chip RAM permitting these addresses to be allocated to external memory instead if so desired 10 2 Block Diagram Figure 10 1 is a block diagram of the on chip RAM Figure 10 1 Block Diagram of On ...

Page 235: ...Bit 7 RAME Description 0 On chip RAM is disabled 1 On chip RAM is enabled Initial value 10 4 Operation 10 4 1 Expanded Modes Modes 1 and 2 If the RAME bit is set to 1 accesses to addresses H FB80 to H FF7F in the H8 329 and H8 328 addresses H FD80 to H FF7F in the H8 327 and addresses H FE80 to H FF7F in the H8 326 are directed to the on chip RAM If the RAME bit is cleared to 0 accesses to these a...

Page 236: ...The H8 329 and H8 327 are available with electrically programmable ROM PROM The PROM version has a PROM mode in which the chip can be programmed with a standard PROM writer The on chip ROM is enabled or disabled depending on the MCU operating mode which is determined by the inputs at the mode pins MD1 and MD0 See table 11 1 Table 11 1 On Chip ROM Usage in Each MCU Mode Mode pins Mode MD1 MD0 On Ch...

Page 237: ...uter functions are halted to allow the on chip PROM to be programmed The programming method is the same as for the HN27C256 To select the PROM mode apply the signal inputs listed in table 11 2 Table 11 2 Selection of PROM Mode Pin Input Mode pin MD1 Low Mode pin MD0 Low STBY pin Low Pins P63 and P64 High H 0002 H 0000 Internal data bus lower 8 bits Internal data bus upper 8 bits H 0003 H 0001 H 7F...

Page 238: ...chip PROM its address range should be specified as H 0000 to H 3FFF H FF data should be specified for unused address areas It is important to limit the program address range to H 0000 to H 7FFF for the H8 329 and to H 0000 to H 3FFF for the H8 327 and specify H FF data for H 8000 or H 4000 and higher addresses If data other than H FF are written by mistake in addresses equal to or greater than H 8...

Page 239: ... EO EO EO EO EO EO EA EA EA EA EA EA EA EA EA OE EA EA EA EA EA CE V V HN27C256 28 pins 1 24 11 12 13 15 16 17 18 19 10 9 8 7 6 5 4 3 25 22 21 23 2 26 27 20 28 14 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 3 4 CC CC CC 0 1 SS SS SS SS SS SS SS 9 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 8 10 11 12 13 14 PP CC H8 329 or H8 327 EPROM Socket Note All pins not listed in this figure should be left open V EO...

Page 240: ...of H8 327 in PROM Mode H 7FFF H 7FFF Address in PROM mode Address in MCU mode On chip PROM H 0000 H 0000 H 3FFF H 3FFF 1 output If this area is read in PROM mode the output data are H FF H 7FFF Address in PROM mode Address in MCU mode H 0000 H 0000 On chip PROM Note 231 ...

Page 241: ...and VCC voltage levels The H8 329 and H8 327 PROM has the same standard read write specifications as the HN27C256 and HN27256 EPROM 11 3 1 Writing and Verifying An efficient high speed programming procedure can be used to write and verify PROM data This procedure writes data quickly without subjecting the chip to voltage stress and without sacrificing data reliability It leaves the data H FF writt...

Page 242: ...ddress 0 n 0 Set read mode VCC 5 0V 0 5V VPP VCC END Yes No Yes No Yes n 25 All addresses read Error No Yes n 1 n Address 1 Address No Last address Write time tPW 1 ms 5 Write tOPW 3n ms Verify OK Set program verify mode VCC 6 0V 0 25V VPP 12 5V 0 3V 233 ...

Page 243: ...Vin 5 25V current EA14 EA0 0 5V OE CE VCC current ICC 40 mA VPP current IPP 40 mA Table 11 6 AC Characteristics when VCC 6 0V 0 25V VPP 12 5V 0 3V Ta 25 C 5 C Measurement Item Symbol Min Typ Max Unit conditions Address setup time tAS 2 µs See figure 11 6 OE setup time tOES 2 µs Data setup time tDS 2 µs Address hold time tAH 0 µs Data hold time tDH 2 µs Data output disable time tDF 130 ns Vpp setup...

Page 244: ...figure 11 6 overwrite programming VCC setup time tVCS 2 µs Data output delay time tOE 0 500 ns Note Input pulse level 0 8V to 2 2V Input rise fall time 20ns Timing reference levels input 1 0V 2 0V output 0 8V 2 0V Figure 11 6 PROM Write Verify Timing OE Write Verify Address Data Input data Output data tVPS tDS tDH tAS tAH tDF VPP VPP VCC tVCS tPW tOPW tOES tOE VCC CE GND 235 ...

Page 245: ...et adapter and chip are correctly mounted in the PROM writer Overcurrent damage to the chip can result if the index marks on the PROM writer socket adapter and chip are not correctly aligned 3 Don t touch the socket adapter or chip while writing Touching either of these can cause contact faults and write errors 11 3 3 Reliability of Written Data An effective way to assure the data holding characte...

Page 246: ...The windowed package enables data to be erased by illuminating the window with ultraviolet light Table 11 7 lists the erasing conditions Table 11 7 Erasing Conditions Item Value Ultraviolet wavelength 253 7 nm Minimum illumination 15W s cm2 The conditions in table 11 7 can be satisfied by placing a 12000µW cm2 ultraviolet lamp 2 or 3 centimeters directly above the chip and leaving it on for about ...

Page 247: ...wear gloves Avoid other possible sources of static charge Avoid friction between the glass window and plastic or other materials that tend to accumulate static charge Be careful when using cooling sprays since they may have a slight ion content Cover the window with an ultraviolet shield label preferably a label including a conductive material Besides protecting the PROM contents from ultraviolet ...

Page 248: ...onditions for entering and leaving the power down modes It also indicates the status of the CPU on chip supporting modules etc in each power down mode Table 12 1 Power Down State Entering CPU Sup I O Exiting Mode procedure Clock CPU Reg s Mod RAM ports methods Sleep Execute Run Halt Held Run Held Held Interrupt mode SLEEP RES instruction STBY Soft Set SSBY bit Halt Halt Held Halt Held Held NMI war...

Page 249: ...re Standby SSBY This bit enables or disables the transition to the software standby mode On recovery from the software standby mode by an external interrupt SSBY remains set to 1 To clear this bit software must write a 0 Bit 7 SSBY Description 0 The SLEEP instruction causes a transition to the sleep mode Initial value 1 The SLEEP instruction causes a transition to the software standby mode Bits 6 ...

Page 250: ...uencies and indicates the recommended settings When the chip is externally clocked the STS bits can be set to any value The minimum value STS2 STS1 STS0 0 is recommended Table 12 3 Times Set by Standby Timer Select Bits Unit ms Settling time System clock frequency MHz STS2 STS1 STS0 states 10 8 6 4 2 1 0 5 0 0 0 8192 0 8 1 0 1 3 2 0 4 1 8 2 16 4 0 0 1 16384 1 6 2 0 2 7 4 1 8 2 16 4 32 8 0 1 0 3276...

Page 251: ...sleep mode when it receives an internal or external interrupt request or a Low input at the RES or STBY pin 1 Wake Up by Interrupt An interrupt releases the sleep mode and starts the CPU s interrupt handling sequence If an interrupt from an on chip supporting module is disabled by the corresponding enable disable bit in the module s control register the interrupt cannot be requested so it cannot w...

Page 252: ...IRQ1 IRQ2 RES or STBY 1 Recovery by External Interrupt When an NMI IRQ0 IRQ1 or IRQ2 request signal is received the clock oscillator begins operating After the waiting time set in the system control register bits STS2 to STS0 clock pulses are supplied to the CPU and on chip supporting modules The CPU executes the interrupt handling sequence for the requested interrupt then returns to the instructi...

Page 253: ...ng the rising edge then executes the SLEEP instruction The chip enters the software standby mode It recovers from the software standby mode on the next rising edge of NMI Figure 12 1 Software Standby Mode when NMI Timing 12 4 4 Application Note The I O ports retain their current states in the software standby mode If a port is in the High output state the current dissipation caused by the High out...

Page 254: ...stem control register should be cleared to 0 before the STBY pin goes Low to disable the on chip RAM during the hardware standby mode 2 Do not change the inputs at the mode pins MD1 MD0 during hardware standby mode Be particularly careful not to let both mode pins go Low in hardware standby mode since that places the chip in PROM mode and increases current dissipation 12 5 2 Recovery from Hardware...

Page 255: ...In the sequence shown first RES goes Low then STBY goes Low at which point the chip enters the hardware standby mode To recover first STBY goes High then after the clock settling time RES goes High Figure 12 2 Hardware Standby Mode Timing Clock pulse generator RES STBY Clock settling time Restart 246 ...

Page 256: ...Pulse Generator 13 2 Oscillator Circuit If an external crystal is connected across the EXTAL and XTAL pins the on chip oscillator circuit generates a clock signal for the system clock divider Alternatively an external clock signal can be applied to the EXTAL pin 1 Connecting an External Crystal Circuit Configuration An external crystal can be connected as in the example in figure 13 2 An AT cut pa...

Page 257: ... 500 120 60 40 30 20 C0 pF 7 pF max Figure 13 3 Equivalent Circuit of External Crystal Note on Board Design When an external crystal is connected other signal lines should be kept away from the crystal circuit to prevent induction from interfering with correct oscillation See figure 13 4 The crystal and its load capacitors should be placed as close as possible to the XTAL and EXTAL pins EXTAL XTAL...

Page 258: ...ternal clock signal can be input as shown in the examples in figure 13 5 In example b the external clock should be held high during standby Figure 13 5 External Clock Input Example EXTAL XTAL External clock input 74HC04 b EXTAL XTAL External clock input Open a Not allowed Signal A Signal B H8 327 XTAL EXTAL CL1 CL2 249 ...

Page 259: ...nput Frequency Double the system clock Ø frequency Duty factor 45 to 55 13 3 System Clock Divider The system clock divider divides the crystal oscillator or external clock frequency by 2 to create the system clock Ø 250 ...

Page 260: ...o AVCC 0 3 V Operating temperature Topr Regular specifications 20 to 75 C Wide range specifications 40 to 85 C Storage temperature Tstg 55 to 125 C Note Exceeding the absolute maximum ratings shown in table 14 1 can permanently destroy the chip 14 2 Electrical Characteristics 14 2 1 DC Characteristics Table 14 2 lists the DC characteristics of the 5V versions of the H8 329 Series Table 14 3 lists ...

Page 261: ...er than 1 and 2 above Input Low voltage RES STBY VIL 0 3 0 5 V 3 MD1 MD0 Input Low voltage Input pins VIL 0 3 0 8 V other than 1 and 3 above Output High All output pins VOH VCC 0 5 V IOH 200µA voltage 3 5 V IOH 1 0mA Output Low All output pins VOL 0 4 V IOL 1 6mA voltage Ports 1 and 2 1 0 V IOL 10 0mA Input leakage RES Iin 10 0 µA Vin 0 5V to current STBY NMI 1 0 µA VCC 0 5V MD1 MD0 P77 P70 1 0 µA...

Page 262: ...tion 2 operation 16 30 mA f 8MHz 20 40 mA f 10MHz Sleep mode 8 15 mA f 6MHz 10 20 mA f 8MHz 12 25 mA f 10MHz Standby modes 3 0 01 5 0 µA Analog supply During A D AICC 0 6 1 5 mA current conversion Waiting 0 01 5 0 µA RAM standby VRAM 2 0 V voltage Notes 1 Connect AVCC to the power supply 5V even when the A D converter is not used 2 Current dissipation values assume that VIH min VCC 0 5V VIL max 0 ...

Page 263: ...utput High All output pins VOH VCC 0 4 V IOH 200µA voltage VCC 0 9 V IOH 1mA Output Low All output pins VOL 0 4 V IOL 0 8mA voltage Ports 1 and 2 0 4 V IOL 1 6mA Input RES Iin 10 0 µA Vin 0 5 to leakage STBY NMI 1 0 µA VCC 0 5V current MD1 MD0 P77 P70 1 0 µA Vin 0 5 to AVCC 0 5V Leakage Ports 1 2 3 ITSI 1 0 µA Vin 0 5 to current in 4 5 6 VCC 0 5V 3 state off state Input Ports 1 2 3 Ip 3 120 µA Vin...

Page 264: ...mA f 5MHz Sleep mode 3 mA f 3MHz 4 8 mA f 5MHz Standby modes 3 0 01 5 0 µA Analog During A D AICC 0 6 1 5 mA supply conversion current Waiting 0 01 5 0 µA RAM backup voltage VRAM 2 0 V in standby modes Notes 1 Connect AVCC to the power supply 3V even when the A D converter is not used 2 Current dissipation values assume that VIH min VCC 0 5V VIL max 0 5V all output pins are in the no load state an...

Page 265: ...5 Allowable Output Current Values 3V Versions Conditions VCC 3 0V 10 AVCC 5 0V 10 VSS AVSS 0V Ta 20 to 75 C Item Symbol Min Typ Max Unit Allowable output Low Ports 1 and 2 IOL 2 mA current per pin Other output pins 1 mA Allowable output Low Ports 1 and 2 total ΣIOL 40 mA current total All output pins 60 mA Allowable output High All output pins IOH 2 mA current per pin Allowable output High Total o...

Page 266: ...2 2 AC Characteristics The AC characteristics of the H8 329 Series are listed in three tables Bus timing parameters are given in table 14 6 control signal timing parameters in table 14 7 and timing parameters of the on chip supporting modules in table 14 8 H8 329 Series Port 2 kΩ Darlington pair Vcc 600 Ω LED Port 1 or 2 H8 329 Series 257 ...

Page 267: ...ss delay time tAD 90 70 60 50 ns Fig 14 4 Address hold time tAH 30 30 25 20 ns Fig 14 4 Address strobe delay time tASD 80 70 60 40 ns Fig 14 4 Write strobe delay time tWSD 80 70 60 50 ns Fig 14 4 Strobe delay time tSD 90 70 60 50 ns Fig 14 4 Write strobe pulse width tWSW 200 200 150 120 ns Fig 14 4 Address setup time 1 tAS1 25 25 20 15 ns Fig 14 4 Address setup time 2 tAS2 105 105 80 65 ns Fig 14 ...

Page 268: ...in Max Min Max Min Max Min Max Unit conditions RES setup time tRESS 300 200 200 200 ns Fig 14 6 RES pulse width tRESW 10 10 10 10 tcyc Fig 14 6 NMI setup time tNMIS 300 150 150 150 ns Fig 14 7 NMI IRQ0 to IRQ2 NMI hold time tNMIH 10 10 10 10 ns Fig 14 7 NMI IRQ0 to IRQ2 Interrupt pulse width tNMIW 300 200 200 200 ns Fig 14 7 for recovery from soft ware standby mode NMI IRQ0 to IRQ2 Crystal oscilla...

Page 269: ...TMR Timer output delay time tTMOD 150 100 100 100 ns Fig 14 12 Timer reset input tTMRS 80 50 50 50 ns Fig 14 14 setup time Timer clock input tTMCS 80 50 50 50 ns Fig 14 13 setup time Timer clock pulse width tTMCWH 1 5 1 5 1 5 1 5 tcyc Fig 14 13 single edge Timer clock pulse width tTMCWL 2 5 2 5 2 5 2 5 tcyc Fig 14 13 both edges SCI Input clock Async tscyc 4 4 4 4 tcyc Fig 14 15 cycle Sync tscyc 6 ...

Page 270: ...perating frequency Ta 20 to 75 C Condition B Condition A 5MHz 6MHz 8MHz 10MHz Item Min Typ Max Min Typ Max Min Typ Max Min Typ Max Unit Resolution 8 8 8 8 8 8 8 8 8 8 8 8 Bits Conversion time single mode 24 4 20 4 15 25 12 2 µs Analog input capacitance 20 20 20 20 pF Allowable signal 10 10 10 10 kΩ source impedance Nonlinearity error 1 1 1 1 LSB Offset error 1 1 1 1 LSB Full scale error 1 1 1 1 LS...

Page 271: ...11 14 3 4 8 Bit Timer Timing Figures 14 12 to 14 14 14 3 5 SCI Timing Figures 14 15 to 14 16 14 3 6 I O Port Timing Figure 14 17 14 3 1 Bus Timing 1 Basic Bus Cycle without Wait States in Expanded Modes Figure 14 4 Basic Bus Cycle without Wait States in Expanded Modes T T1 tcyc 2 T3 tCH tCL tAD tCr tASD tACC tRDS tWSD tAS2 tWDD tWDS tWDH tAH tWSW tRDH tAH tSD Ø A15 to A0 WR D7 to D0 Read D7 to D0 ...

Page 272: ...4 5 Basic Bus Cycle with 1 Wait State in Expanded Modes Modes 1 and 2 14 3 2 Control Signal Timing 1 Reset Input Timing Figure 14 6 Reset Input Timing Ø AS RD WR WAIT D7 to D0 Read A15 to A0 D7 to D0 Write T1 T2 TW T3 tWTS tWTH tWTS tWTH Ø RES tRESS tRESS tRESW 263 ...

Page 273: ... 2 Interrupt Input Timing Figure 14 7 Interrupt Input Timing Ø IRQL Level NMI IRQi t t t NMI IRQE Edge NMIS NMIS NMIH tNMIW Note i 0 to 2 IRQE IRQi when edge sensed IRQL IRQi when level sensed 264 ...

Page 274: ... 3 Clock Settling Timing Ø VCC RES STBY tOSC1 tOSC1 Figure 14 8 Clock Setting Timing 265 ...

Page 275: ...Timing for Recovery from Software Standby Mode 14 3 3 16 Bit Free Running Timer Timing 1 Free Running Timer Input Output Timing Figure 14 10 Free Running Timer Input Output Timing OSC2 Ø NMI IRQi i 0 1 2 t Ø Compare match FTIA FTIB FTIC FTID FTOA FTOB Free running timer counter tFTOD tFTIS 266 ...

Page 276: ...ee Running Timer 14 3 4 8 Bit Timer Timing 1 8 Bit Timer Output Timing Figure 14 12 8 Bit Timer Output Timing 2 8 Bit Timer Clock Input Timing Figure 14 13 8 Bit Timer Clock Input Timing Ø FTCI tFTCS tFTCWL tFTCWH Ø Timer counter Compare match TMO0 TMO1 tTMOD Ø tTMCS tTMCS tTMCWL tTMCWH TMCI0 TMCI1 267 ...

Page 277: ...Reset Input Timing 14 3 5 Serial Communication Interface Timing 1 SCI Input Output Timing Figure 14 15 SCI Input Output Timing Synchronous Mode N H 00 Ø Timer counter tTMRS TMRI0 TMRI1 tScyc tTXD tRXS tRXH Serial clock SCK Transmit data TxD Receive data RxD 268 ...

Page 278: ... Timing Figure 14 16 SCI Input Clock Timing 14 3 6 I O Port Timing Figure 14 17 I O Port Input Output Timing t SCKW t Scyc SCK T1 T2 T3 tPRS tPRH tPWD Port 1 to Port 7 Input Port 1 to Port 6 Output Ø Note Except P46 269 ...

Page 279: ...270 ...

Page 280: ...o flag in CCR V V overflow flag in CCR C C carry flag in CCR PC Program counter SP Stack pointer xx 3 8 16 Immediate data 3 8 or 16 bits d 8 16 Displacement 8 or 16 bits aa 8 16 Absolute address 8 or 16 bits Addition Subtraction Multiplication Division AND logical OR logical Exclusive OR logical Move Not Condition Code Notation Modified according to the instruction result Undetermined unpredictabl...

Page 281: ... W Rs Rd W Rs16 Rd16 2 0 4 MOV W d 16 Rs Rd W d 16 Rs16 Rd16 4 0 6 MOV W Rs Rd W Rs16 Rd16 2 0 6 Rs16 2 Rs16 MOV W aa 16 Rd W aa 16 Rd16 4 0 6 MOV W Rs Rd W Rs16 Rd16 2 0 4 MOV W Rs d 16 Rd W Rs16 d 16 Rd16 4 0 6 MOV W Rs Rd W Rd16 2 Rd16 2 0 6 Rs16 Rd16 MOV W Rs aa 16 W Rs16 aa 16 4 0 6 POP Rd W SP Rd16 2 0 6 SP 2 SP PUSH Rs W SP 2 SP 2 0 6 Rs16 SP MOVFPE aa 16 Rd B Not supported by the H8 329 Se...

Page 282: ... Rd8 decimal adjust Rd8 2 2 SUB B Rs Rd B Rd8 Rs8 Rd8 2 2 SUB W Rs Rd W Rd16 Rs16 Rd16 2 2 SUBX B xx 8 Rd B Rd8 xx 8 C Rd8 2 2 SUBX B Rs Rd B Rd8 Rs8 C Rd8 2 2 SUBS W 1 Rd W Rd16 1 Rd16 2 2 SUBS W 2 Rd W Rd16 2 Rd16 2 2 DEC B Rd B Rd8 1 Rd8 2 2 DAS B Rd B Rd8 decimal adjust Rd8 2 2 No of states I H N Z V C Operand size Addressing mode instruction length Mnemonic Operation Condition code Table A 1 ...

Page 283: ...BSET xx 3 Rd B xx 3 of Rd16 1 4 8 BSET xx 3 aa 8 B xx 3 of aa 8 1 4 8 BSET Rn Rd B Rn8 of Rd8 1 2 2 BSET Rn Rd B Rn8 of Rd16 1 4 8 C 0 No of states I H N Z V C 0 C 0 C C 0 C 0 C C b0 b7 b0 b7 b0 b7 b0 b7 b0 b7 b0 b7 b0 b7 b0 b7 Operand size Addressing mode instruction length Mnemonic Operation Condition code Table A 1 Instruction Set cont xx 8 16 Rn Rn d 16 Rn Rn Rn aa 8 16 d 8 PC aa ...

Page 284: ... Rn8 of Rd16 Z 4 6 BTST Rn aa 8 B Rn8 of aa 8 Z 4 6 BLD xx 3 Rd B xx 3 of Rd8 C 2 2 BLD xx 3 Rd B xx 3 of Rd16 C 4 6 BLD xx 3 aa 8 B xx 3 of aa 8 C 4 6 BILD xx 3 Rd B xx 3 of Rd8 C 2 2 BILD xx 3 Rd B xx 3 of Rd16 C 4 6 BILD xx 3 aa 8 B xx 3 of aa 8 C 4 6 BST xx 3 Rd B C xx 3 of Rd8 2 2 BST xx 3 Rd B C xx 3 of Rd16 4 8 BST xx 3 aa 8 B C xx 3 of aa 8 4 No of states Operand size Addressing mode instr...

Page 285: ...8 B C xx 3 of aa 8 C 4 6 BRA d 8 BT d 8 PC PC d 8 2 4 BRN d 8 BF d 8 PC PC 2 2 4 BHI d 8 if condition C Z 0 2 4 BLS d 8 is true then C Z 1 2 4 BCC d 8 BHS d 8 PC PC d 8 C 0 2 4 BCS d 8 BLO d 8 else next C 1 2 4 BNE d 8 Z 0 2 4 BEQ d 8 Z 1 2 4 BVC d 8 V 0 2 4 BVS d 8 V 1 2 No of states I H N Z V C Operand size Addressing mode instruction length Mnemonic Operation Condition code Table A 1 Instructio...

Page 286: ...are located in on chip memory Set to 1 when there is a carry or borrow from bit 11 otherwise cleared to 0 If the result is zero the previous value of the flag is retained otherwise the flag is cleared to 0 Set to 1 if decimal adjustment produces a carry otherwise cleared to 0 The number of states required for execution is 4n 8 n value of R4L These instructions are not supported by the H8 329 Serie...

Page 287: ...first instruction word Some pairs of instructions have identical first bytes These instructions are differentiated by the first bit of the second byte bit 7 of the first instruction word Instruction when first bit of byte 2 bit 7 of first instruction word is 0 Instruction when first bit of byte 2 bit 7 of first instruction word is 1 278 ...

Page 288: ...OTXL ROTL ROTXR ROTR NOT NEG OR XOR AND SUB DEC SUBS CMP SUBX DAS MOV BRA BRN BHI BLS BCC BCS BNE BEQ BVS BPL BMI BLT BGT BLE MULXU DIVXU RTS BSR RTE JMP JSR BVC BGE BSET BNOT BCLR BTST MOV MOV EEPMOV ADD ADDX CMP SUBX OR XOR AND MOV BXOR BIXOR BAND BIAND BOR BIOR BLD BILD BST BIST Bit manipulation instruction 1 2 2 2 2 Table A 2 Operation Code Map 287 ...

Page 289: ... N SN Examples Mode 1 on chip ROM disabled stack located in external memory 1 wait state inserted in external memory access 1 BSET 0 FFC7 From table A 4 I L 2 J K M N 0 From table A 3 SI 8 SL 3 Number of states required for execution 2 8 2 3 22 2 JSR 30 From table A 4 I 2 J K 1 L M N 0 From table A 3 SI SJ SK 8 Number of states required for execution 2 8 1 8 1 8 32 Table A 3 Number of States Taken...

Page 290: ... 8 Rd 1 ADDX B Rs Rd 1 AND AND B xx 8 Rd 1 AND B Rs Rd 1 ANDC ANDC xx 8 CCR 1 BAND BAND xx 3 Rd 1 BAND xx 3 Rd 2 1 BAND xx 3 aa 8 2 1 Bcc BRA d 8 BT d 8 2 BRN d 8 BF d 8 2 BHI d 8 2 BLS d 8 2 BCC d 8 BHS d 8 2 BCS d 8 BLO d 8 2 BNE d 8 2 BEQ d 8 2 BVC d 8 2 BVS d 8 2 BPL d 8 2 BMI d 8 2 BGE d 8 2 BLT d 8 2 BGT d 8 2 BLE d 8 2 BCLR BCLR xx 3 Rd 1 BCLR xx 3 Rd 2 2 BCLR xx 3 aa 8 2 2 BCLR Rn Rd 1 BCL...

Page 291: ...BIOR xx 3 Rd 1 BIOR xx 3 Rd 2 1 BIOR xx 3 aa 8 2 1 BIST BIST xx 3 Rd 1 BIST xx 3 Rd 2 2 BIST xx 3 aa 8 2 2 BIXOR BIXOR xx 3 Rd 1 BIXOR xx 3 Rd 2 1 BIXOR xx 3 aa 8 2 1 BLD BLD xx 3 Rd 1 BLD xx 3 Rd 2 1 BLD xx 3 aa 8 2 1 BNOT BNOT xx 3 Rd 1 BNOT xx 3 Rd 2 2 BNOT xx 3 aa 8 2 2 BNOT Rn Rd 1 BNOT Rn Rd 2 2 BNOT Rn aa 8 2 2 BOR BOR xx 3 Rd 1 BOR xx 3 Rd 2 1 BOR xx 3 aa 8 2 1 BSET BSET xx 3 Rd 1 BSET xx ...

Page 292: ...2 1 BTST Rn aa 8 2 1 BXOR BXOR xx 3 Rd 1 BXOR xx 3 Rd 2 1 BXOR xx 3 aa 8 2 1 CMP CMP B xx 8 Rd 1 CMP B Rs Rd 1 CMP W Rs Rd 1 DAA DAA B Rd 1 DAS DAS B Rd 1 DEC DEC B Rd 1 DIVXU DIVXU B Rs Rd 1 12 EEPMOV EEPMOV 2 2n 2 1 INC INC B Rd 1 JMP JMP Rn 2 JMP aa 16 2 2 JMP aa 8 2 1 2 JSR JSR Rn 2 1 JSR aa 16 2 1 2 JSR aa 8 2 1 1 LDC LDC xx 8 CCR 1 LDC Rs CCR 1 MOV MOV B xx 8 Rd 1 MOV B Rs Rd 1 MOV B Rs Rd 1...

Page 293: ...1 MOV B Rs aa 16 2 1 MOV W xx 16 Rd 2 MOV W Rs Rd 1 MOV W Rs Rd 1 1 MOV W d 16 Rs Rd 2 1 MOV W Rs Rd 1 1 2 MOV W aa 16 Rd 2 1 MOV W Rs Rd 1 1 MOV W Rs d 16 Rd 2 1 MOV W Rs Rd 1 1 2 MOV W Rs aa 16 2 1 MOVFPE MOVFPE aa 16 Rd Not supported MOVTPE MOVTPE Rs aa 16 MULXU MULXU Rs Rd 1 12 NEG NEG B Rd 1 NOP NOP 1 NOT NOT B Rd 1 OR OR B xx 8 Rd 1 OR B Rs Rd 1 ORC ORC xx 8 CCR 1 POP POP Rd 1 1 2 PUSH PUSH ...

Page 294: ...ration Instruction Mnemonic I J K L M N RTE RTE 2 2 2 RTS RTS 2 1 2 SHAL SHAL B Rd 1 SHAR SHAR B Rd 1 SHLL SHLL B Rd 1 SHLR SHLR B Rd 1 SLEEP SLEEP 1 STC STC CCR Rd 1 SUB SUB B Rs Rd 1 SUB W Rs Rd 1 SUBS SUBS W 1 2 Rd 1 SUBX SUBX B xx 8 Rd 1 SUBX B Rs Rd 1 XOR XOR B xx 8 Rd 1 XOR B Rs Rd 1 XORC XORC xx 8 CCR 1 Note All values left blank are zero 285 ...

Page 295: ...H 89 H 8A H 8B H 8C H 8D H 8E H 8F H 90 TIER ICIAE ICIBE ICICE ICIDE OCIAE OCIBE OVIE FRT H 91 TCSR ICFA ICFB ICFC ICFD OCFA OCFB OVF CCLRA H 92 FRC H H 93 FRC L H 94 OCRA H OCRB H H 95 OCRA L OCRB L H 96 TCR IEDGA IEDGB IEDGC IEDGD BUFEA BUFEB CKS1 CKS0 H 97 TOCR OCRS OEA OEB OLVLA OLVLB H 98 ICRA H H 99 ICRA L H 9A ICRB H H 9B ICRB L H 9C ICRC H H 9D ICRC L H 9E ICRD H H 9F ICRD L Continued on n...

Page 296: ... P2DDR P27DDR P26DDR P25DDR P24DDR P23DDR P22DDRP21DDR P20DDR Port 2 H B2 P1DR P17 P16 P15 P14 P13 P12 P11 P10 Port 1 H B3 P2DR P27 P26 P25 P24 P23 P22 P21 P20 Port 2 H B4 P3DDR P37DDR P36DDR P35DDR P34DDR P33DDR P32DDRP31DDR P30DDR Port 3 H B5 P4DDR P47DDR P46DDR P45DDR P44DDR P43DDR P42DDRP41DDR P40DDR Port 4 H B6 P3DR P37 P36 P35 P34 P33 P32 P31 P30 Port 3 H B7 P4DR P47 P46 P45 P44 P43 P42 P41 ...

Page 297: ...CKS0 TMR0 H C9 TCSR CMFB CMFA OVF OS3 OS2 OS1 OS0 H CA TCORA H CB TCORB H CC TCNT H CD H CE H CF H D0 TCR CMIEB CMIEA OVIE CCLR1 CCLR0 CKS2 CKS1 CKS0 TMR1 H D1 TCSR CMFB CMFA OVF OS3 OS2 OS1 OS0 H D2 TCORA H D3 TCORB H D4 TCNT H D5 H D6 H D7 H D8 SMR C A CHR PE O E STOP MP CKS1 CKS0 SCI H D9 BRR H DA SCR TIE RIE TE RE MPIE TEIE CKE1 CKE0 H DB TDR H DC SSR TDRE RDRF ORER FER PER TEND MPB MPBT H DD ...

Page 298: ... 2 Bit 1 Bit 0 Module H E0 ADDRA A D H E1 H E2 ADDRB H E3 H E4 ADDRC H E5 H E6 ADDRD H E7 H E8 ADCSR ADF ADIE ADST SCAN CKS CH2 CH1 CH0 H E9 H EA ADCR TRGE CHS H EB H EC H ED H EE H EF H F0 H F1 H F2 H F3 H F4 H F5 H F6 H F7 H F8 H F9 H FA H FB H FC H FD H FE H FF Note A D Analog to Digital converter 289 ...

Page 299: ...errupt request A is enabled Output compare interrupt request A is disabled 1 0 Input Capture Interrupt D Enable Input capture interrupt request D is enabled Input capture interrupt request D is disabled 1 0 3 OCIAE 0 R W 2 OCIBE 0 R W 1 OVIE 0 R W 0 1 TIER Timer Interrupt Enable Register H FF90 FRT Bit No Initial value Type of access permitted R W R W Abbreviation of register name Register name Ad...

Page 300: ... Interrupt A Enable 0 Output compare interrupt request A is disabled 1 Output compare interrupt request A is enabled Input Capture Interrupt D Enable 0 Input capture interrupt request D is disabled 1 Input capture interrupt request D is enabled Input Capture Interrupt C Enable 0 Input capture interrupt request C is disabled 1 Input capture interrupt request C is enabled Input Capture Interrupt B E...

Page 301: ...et when FRC OCRB Output Compare Flag A 0 Cleared when CPU reads OCFA 1 then writes 0 in OCFA 1 Set when FRC OCRA Input Capture Flag D 0 Cleared when CPU reads ICFD 1 then writes 0 in ICFD 1 Set by FTID input Input Capture Flag C 0 Cleared when CPU reads ICFC 1 then writes 0 in ICFC 1 Set by FTIC input Input Capture Flag B 0 Cleared when CPU reads ICFB 1 then writes 0 in ICFB 1 Set when FTIB input ...

Page 302: ...er A H FF94 H FF95 FRT Bit 7 6 5 4 3 2 1 0 Initial value 1 1 1 1 1 1 1 1 Read Write R W R W R W R W R W R W R W R W Continually compared with FRC OCFA is set to 1 when OCRA FRC OCRB H and L Output Compare Register B H FF94 H FF95 FRT Bit 7 6 5 4 3 2 1 0 Initial value 1 1 1 1 1 1 1 1 Read Write R W R W R W R W R W R W R W R W Continually compared with FRC OCFB is set to 1 when OCRB FRC 293 ...

Page 303: ... Buffer Enable B 0 ICRD is used for input capture D 1 ICRD is buffer register for input capture B Buffer Enable A 0 ICRC is used for input capture C 1 ICRC is buffer register for input capture A Input Edge Select D 0 Falling edge of FTID is valid 1 Rising edge of FTID is valid Input Edge Select C 0 Falling edge of FTIC is valid 1 Rising edge of FTIC is valid Input Edge Select B 0 Falling edge of F...

Page 304: ... output 1 Compare match A causes 1 output Output Enable B 0 Output compare B output is disabled 1 Output compare B output is enabled Output Enable A 0 Output compare A output is disabled 1 Output compare A output is enabled Output Compare Register Select 0 The CPU can access OCRA 1 The CPU can access OCRB ICRA H and L Input Capture Register A H FF98 H FF99 FRT Bit 7 6 5 4 3 2 1 0 Initial value 0 0...

Page 305: ...pture Register C H FF9C H FF9D FRT Bit 7 6 5 4 3 2 1 0 Initial value 0 0 0 0 0 0 0 0 Read Write R R R R R R R R Contains FRC count captured on FTIC input or old ICRA value in buffer mode ICRD H and L Input Capture Register D H FF9E H FF9F FRT Bit 7 6 5 4 3 2 1 0 Initial value 0 0 0 0 0 0 0 0 Read Write R R R R R R R R Contains FRC count captured on FTID input or old ICRB value in buffer mode 296 ...

Page 306: ...ort 2 Bit 7 6 5 4 3 2 1 0 P27PCR P26PCR P25PCR P24PCR P23PCR P22PCR P21PCR P20PCR Initial value 0 0 0 0 0 0 0 0 Read Write R W R W R W R W R W R W R W R W Port 2 Input Pull Up Control 0 Input pull up transistor is off 1 Input pull up transistor is on P3PCR Port 3 Input Pull Up Control Register H FFAE Port 3 Bit 7 6 5 4 3 2 1 0 P37PCR P36PCR P35PCR P34PCR P33PCR P32PCR P31PCR P30PCR Initial value 0...

Page 307: ...Initial value 1 1 1 1 1 1 1 1 Read Write Modes 2 and 3 Initial value 0 0 0 0 0 0 0 0 Read Write W W W W W W W W Port 1 Input Output Control 0 Input port 1 Output port P1DR Port 1 Data Register H FFB2 Port 1 Bit 7 6 5 4 3 2 1 0 P17 P16 P15 P14 P13 P12 P11 P10 Initial value 0 0 0 0 0 0 0 0 Read Write R W R W R W R W R W R W R W R W 298 ...

Page 308: ...Input Output Control 0 Input port 1 Output port P2DR Port 2 Data Register H FFB3 Port 2 Bit 7 6 5 4 3 2 1 0 P27 P26 P25 P24 P23 P22 P21 P20 Initial value 0 0 0 0 0 0 0 0 Read Write R W R W R W R W R W R W R W R W P3DDR Port 3 Data Direction Register H FFB4 Port 3 Bit 7 6 5 4 3 2 1 0 P37DDR P36DDR P35DDR P34DDR P33DDR P32DDR P31DDR P30DDR Initial value 0 0 0 0 0 0 0 0 Read Write W W W W W W W W Por...

Page 309: ...alue 0 0 0 0 0 0 0 0 Read Write W W W W W W W W Port 4 Input Output Control 0 Input port 1 Output port P4DR Port 4 Data Register H FFB7 Port 4 Bit 7 6 5 4 3 2 1 0 P47 P46 P45 P44 P43 P42 P41 P40 Initial value 0 0 0 0 0 0 0 Read Write R W R W R W R W R W R W R W R W Note Determined by the level at pin P46 P5DDR Port 5 Data Direction Register H FFB8 Port 5 Bit 7 6 5 4 3 2 1 0 P52DDR P51DDR P50DDR In...

Page 310: ...tial value 0 0 0 0 0 0 0 0 Read Write W W W W W W W W Port 6 Input Output Control 0 Input port 1 Output port P6DR Port 6 Data Register H FFBB Port 6 Bit 7 6 5 4 3 2 1 0 P67 P66 P65 P64 P63 P62 P61 P60 Initial value 0 0 0 0 0 0 0 0 Read Write R W R W R W R W R W R W R W R W P7DR Port 7 Data Register H FFBE Port 7 Bit 7 6 5 4 3 2 1 0 P77 P76 P75 P74 P73 P72 P71 P70 Initial value Read Write R R R R R...

Page 311: ...2 1 0 SSBY STS2 STS1 STS0 NMIEG RAME Initial value 0 0 0 0 1 0 1 1 Read Write R W R W R W R W R W R W RAM Enable 0 On chip RAM is disabled 1 On chip RAM is enabled NMI Edge 0 Falling edge of NMI is detected 1 Rising edge of NMI is detected Standby Timer Select 0 0 0 Clock settling time 8192 states 0 0 1 Clock settling time 16384 states 0 1 0 Clock settling time 32768 states 0 1 1 Clock settling ti...

Page 312: ...rol Register H FFC6 System Control Bit 7 6 5 4 3 2 1 0 IRQ2SC IRQ1SC IRQ0SC Initial value 1 1 1 1 1 0 0 0 Read Write R W R W R W IRQ0 to IRQ2 Sense Control 0 IRQi is level sensed active Low 1 IRQi is edge sensed falling edge IER IRQ Enable Register H FFC7 System Control Bit 7 6 5 4 3 2 1 0 IRQ2E IRQ1E IRQ0E Initial value 1 1 1 1 1 0 0 0 Read Write R W R W R W IRQ0 to IRQ2 Enable 0 IRQi is disabled...

Page 313: ...nal clock falling edge 1 0 0 Timer stopped 1 0 1 External clock rising edge 1 1 0 External clock falling edge 1 1 1 External clock rising and falling edges Counter Clear 0 0 Counter is not cleared 0 1 Cleared by compare match A 1 0 Cleared by compare match B 1 1 Cleared on rising edge of external reset input Timer Overflow Interrupt Enable 0 Overflow interrupt request is disabled 1 Overflow interr...

Page 314: ...Output 0 on compare match B 1 0 Output 1 on compare match B 1 1 Invert toggle output on compare match B Timer Overflow Flag 0 Cleared when CPU reads OVF 1 then writes 0 in OVF 1 Set when TCNT changes from H FF to H 00 Compare Match Flag A 0 Cleared when CPU reads CMFA 1 then writes 0 in CMFA 1 Set when TCNT TCORA Compare Match Flag B 0 Cleared from when CPU reads CMFB 1 then writes 0 in CMFB 1 Set...

Page 315: ...it is set to 1 when TCORA TCNT TCORB Time Constant Register B H FFCB TMR0 Bit 7 6 5 4 3 2 1 0 Initial value 1 1 1 1 1 1 1 1 Read Write R W R W R W R W R W R W R W R W The CMFB bit is set to 1 when TCORB TCNT TCNT Timer Counter H FFCC TMR0 Bit 7 6 5 4 3 2 1 0 Initial value 0 0 0 0 0 0 0 0 Read Write R W R W R W R W R W R W R W R W Count value 306 ...

Page 316: ...rnal clock falling edge 1 0 0 Timer stopped 1 0 1 External clock rising edge 1 1 0 External clock falling edge 1 1 1 External clock rising and falling edges Counter Clear 0 0 Counter is not cleared 0 1 Cleared by compare match A 1 0 Cleared by compare match B 1 1 Cleared on rising edge of external reset input Timer Overflow Interrupt Enable 0 Overflow interrupt request is disabled 1 Overflow inter...

Page 317: ...ared to 0 output is disabled TCORA Time Constant Register A H FFD2 TMR1 Bit 7 6 5 4 3 2 1 0 Initial value 1 1 1 1 1 1 1 1 Read Write R W R W R W R W R W R W R W R W Note Bit functions are the same as for TMR0 TCORB Time Constant Register B H FFD3 TMR1 Bit 7 6 5 4 3 2 1 0 Initial value 1 1 1 1 1 1 1 1 Read Write R W R W R W R W R W R W R W R W Note Bit functions are the same as for TMR0 TCNT Timer ...

Page 318: ... 64 clock Multiprocessor Mode 0 Multiprocessor function disabled 1 Multiprocessor format selected Stop Bit Length 0 One stop bit 1 Two stop bits Parity Mode 0 Even parity 1 Odd parity Parity Enable 0 Transmit No parity bit added Receive Parity bit not checked 1 Transmit Parity bit added Receive Parity bit checked Character Length 0 8 Bit data length 1 7 Bit data length Communication Mode 0 Asynchr...

Page 319: ...BRR Bit Rate Register H FFD9 SCI Bit 7 6 5 4 3 2 1 0 Initial value 1 1 1 1 1 1 1 1 Read Write R W R W R W R W R W R W R W R W Constant that determines the bit rate 310 ...

Page 320: ...TSR empty interrupt request is enabled Multiprocessor Interrupt Enable 0 Multiprocessor receive interrupt function is disabled 1 Multiprocessor receive interrupt function is enabled Receive Enable 0 Receive disabled 1 Receive enabled Transmit Enable 0 Transmit disabled 1 Transmit enabled Receive Interrupt Enable 0 Receive interrupt and receive error interrupt requests are disabled 1 Receive interr...

Page 321: ...TDR Transmit Data Register H FFDB SCI Bit 7 6 5 4 3 2 1 0 Initial value 1 1 1 1 1 1 1 1 Read Write R W R W R W R W R W R W R W R W Transmit data 312 ...

Page 322: ...parity error occurs parity of receive data does not match parity selected by O E bit in SMR Framing Error 0 Cleared when CPU reads FER 1 then writes 0 in FER 1 Set when a framing error occurs stop bit is 0 Overrun Error 0 Cleared when CPU reads ORER 1 then writes 0 in ORER 1 Set when an overrun error occurs next data is completely received while RDRF bit is set to 1 Receive Data Register Full 0 Cl...

Page 323: ... 3 2 1 0 Initial value 0 0 0 0 0 0 0 0 Read Write R R R R R R R R Receive data ADDRn A D Data Register n n A B C D H FFE0 H FFE2 A D H FFE4 H FFE6 Bit 7 6 5 4 3 2 1 0 Initial value 0 0 0 0 0 0 0 0 Read Write R R R R R R R R A D conversion result 314 ...

Page 324: ... mode A D Start 0 A D conversion is halted 1 1 Single mode One A D conversion is performed then this bit is automatically cleared to 0 2 Scan mode A D conversion starts and continues cyclically on all selected channels until 0 is written in this bit A D Interrupt Enable 0 The A D interrupt request ADI is disabled 1 The A D interrupt request ADI is enabled A D End Flag 0 Cleared from 1 to 0 when CP...

Page 325: ... A D Bit 7 6 5 4 3 2 1 0 TRGE CHS Initial value 0 1 1 1 1 1 1 0 Read Write R W R W Channel Select Reserved bit Trigger Enable 0 ADTRG is disabled 1 ADTRG is enabled A D conversion can be started by external trigger or by software 316 ...

Page 326: ...P37 P30 1 3 State 3 State 3 State 3 State D7 D0 D7 D0 2 3 Prev state Prev state I O port P47 WAIT 1 3 State 3 State 3 State 3 State WAIT 2 3 Prev state Prev state I O port P46 Ø 1 Clock 3 State High Clock Clock 2 output output output 3 3 State High if Clock output Clock output DDR 1 if DDR 1 if DDR 1 3 state if 3 state if input port if DDR 0 DDR 0 DDR 0 Notes 1 3 State High impedance state 2 Prev ...

Page 327: ...te Prev state I O port 2 3 P77 P70 1 3 State 3 State 3 State 3 State Input port 2 3 Notes 1 3 State High impedance state 2 Prev state Previous state Input ports are in the high impedance state with the MOS pull up on if PCR 1 Output ports hold their previous output level 3 I O port Direction depends on the data direction DDR bit Note that these pins may also be used by the on chip supporting modul...

Page 328: ... before the STBY signal goes low as shown below RES must remain low until STBY goes low minimum delay from STBY low to RES high 0 ns 2 When the RAME bit in SYSCR is set to 1 or it is not necessary to retain RAM contents RES does not have to be driven low as in 1 Timing of Recovery From Hardware Standby Mode Drive the RES signal low approximately 100 ns before STBY goes high STBY RES t 10 t 1 cyc t...

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