Hitachi H8/326 Series, Hardware Manual

Page: 269 / 328

Table 14-8. Timing Conditions of On-Chip Supporting Modules
Condition A: V
CC
= 5.0V ±10%, V
SS
= 0V, Ø = 0.5MHz to maximum operating frequency,
Ta = –20 to 75˚C (regular specifications),
Ta = –40 to 85˚C (wide-range specifications)
Condition B: V
CC
= 3.0V ±10%, V
SS
= 0V, Ø = 0.5MHz to maximum operating frequency,
Ta = –20 to 75˚C
Condition B Condition A
5MHz 6MHz 8MHz 10MHz Measurement
Item Symbol Min Max Min Max Min Max Min Max Unit conditions
FRT Timer output delay time t
FTOD
– 150 – 100 – 100 – 100 ns Fig. 14-10
Timer input setup time t
FTIS
80 – 50 – 50 – 50 – ns Fig. 14-10
Timer clock input t
FTCS
80 – 50 – 50 – 50 – ns Fig. 14-11
setup time
Timer clock pulse width t
FTCWH
1.5 – 1.5 – 1.5 – 1.5 – tcyc Fig. 14-11
t
FTCWL
TMR Timer output delay time t
TMOD
– 150 – 100 – 100 – 100 ns Fig. 14-12
Timer reset input t
TMRS
80 – 50 – 50 – 50 – ns Fig. 14-14
setup time
Timer clock input t
TMCS
80 – 50 – 50 – 50 – ns Fig. 14-13
setup time
Timer clock pulse width t
TMCWH
1.5 – 1.5 – 1.5 – 1.5 – t
cyc
Fig. 14-13
(single edge)
Timer clock pulse width t
TMCWL
2.5 – 2.5 – 2.5 – 2.5 – t
cyc
Fig. 14-13
(both edges)
SCI Input clock (Async) t
scyc
4 – 4 – 4 – 4 – t
cyc
Fig. 14-15
cycle (Sync) t
scyc
6 – 6 – 6 – 6 – t
cyc
Fig. 14-15
Transmit data delay t
TXD
– 200 – 100 – 100 – 100 ns Fig. 14-15
time (Sync)
Receive data setup time t
RXS
150 – 100 – 100 – 100 – ns Fig. 14-15
(Sync)
Receive data hold time t
RXH
150 – 100 – 100 – 100 – ns Fig. 14-15
(Sync)
Input clock pulse width t
SCKW
0.4 0.6 0.4 0.6 0.4 0.6 0.4 0.6 t
scyc
Fig. 14-16
Ports Output data delay time t
PWD
– 150 – 100 – 100 – 100 ns Fig. 14-17
Input data setup time t
PRS
80 – 50 – 50 – 50 – ns Fig. 14-17
Input data hold time t
PRH
80 – 50 – 50 – 50 – ns Fig. 14-17
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