Hitachi H8/326 Series, Hardware Manual

Page: 267 / 328

Table 14-6. Bus Timing
Condition A: V
CC
= 5.0V ±10%, V
SS
= 0V, Ø = 0.5MHz to maximum operating frequency,
Ta = –20 to 75˚C (regular specifications),
Ta = –40 to 85˚C (wide-range specifications)
Condition B: V
CC
= 3.0V ±10%, V
SS
= 0V, Ø = 0.5MHz to maximum operating frequency,
Ta = –20 to 75˚C
Condition B Condition A
5MHz 6MHz 8MHz 10MHz Measurement
Item Symbol Min Max Min Max Min Max Min Max Unit conditions
Clock cycle time t
cyc
200 2000 166.7 2000 125 2000 100 2000 ns Fig. 14-4
Clock pulse width Low t
CL
70 – 65 – 45 – 35 – ns Fig. 14-4
Clock pulse width High t
CH
70 – 65 – 45 – 35 – ns Fig. 14-4
Clock rise time t
Cr
– 25 – 15 – 15 – 15 ns Fig. 14-4
Clock fall time t
Cf
– 25 – 15 – 15 – 15 ns Fig. 14-4
Address delay time t
AD
– 90 – 70 – 60 – 50 ns Fig. 14-4
Address hold time t
AH
30 – 30 – 25 – 20 – ns Fig. 14-4
Address strobe delay time t
ASD
– 80 – 70 – 60 – 40 ns Fig. 14-4
Write strobe delay time t
WSD
– 80 – 70 – 60 – 50 ns Fig. 14-4
Strobe delay time t
SD
– 90 – 70 – 60 – 50 ns Fig. 14-4
Write strobe pulse width* t
WSW
200 – 200 – 150 – 120 – ns Fig. 14-4
Address setup time 1* t
AS1
25 – 25 – 20 – 15 – ns Fig. 14-4
Address setup time 2* t
AS2
105 – 105 – 80 – 65 – ns Fig. 14-4
Read data setup time t
RDS
90 – 70 – 50 – 35 – ns Fig. 14-4
Read data hold time t
RDH
0 – 0 – 0 – 0 – ns Fig. 14-4
Read data access time* t
ACC
– 300 – 270 – 210 – 170 ns Fig. 14-4
Write data delay time t
WDD
– 125 – 85 – 75 – 75 ns Fig. 14-4
Write data setup time t
WDS
10 – 20 – 10 – 5 – ns Fig. 14-4
Write data hold time t
WDH
30 – 30 – 25 – 20 – ns Fig. 14-4
Wait setup time t
WTS
60 – 40 – 40 – 40 – ns Fig. 14-5
Wait hold time t
WTH
20 – 10 – 10 – 10 – ns Fig. 14-5
Note: * Values at maximum operating frequency
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