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F650 DIGITAL BAY CONTROLLER
GEK-106310-AF
5.5 CONTROL ELEMENTS
CHAPTER 5: SETPOINTS
The following figure shows the logic scheme for the breaker failure element:
Figure 5-30: Logic scheme for 50BF
The breaker failure element has three levels. The first one is called “Retrip” or “Supervision”. This operation level can be
used to give a signal to the breaker on which the initial opening has been executed. This is sometimes a usual practice; 50
milliseconds after the trip signal, a retrip signal is sent to the breaker.
Besides the supervision or retrip level, there are two additional levels, known as “Hiset” and “Lowset”. These two levels,
together with their time delays, allow executing complex protection schemes. Additionally to these two supervision levels,
there is a second time stage called “second step”.
Operation of breaker failure elements by level (supervision, hi set and lo set) is produced when the current level is higher
than the set current for the pickup of each level during the time set in the corresponding delay setting.
High and low levels constitute a second step level; for the pickup of this second level, only the pickup of any of the two
levels (hiset and loset) is required. For the element pickup to dropout it is required that the current is under the pickup levels
of both hiset and loset settings. Once the second level time delay has expired, a “Second Step” trip signal is issued.
50BF element incorporates also a no current tripping element, and an internal arc element. The no-current trip element is
governed only by the status of the breaker auxiliary contact; once the external breaker failure initiation signal is received,
if the breaker status does not change to open during the set time in the element (No Current Delay), the corresponding
breaker failure signal is issued (BKR FAIL NO CURRENT),
The internal arc element inside the breaker failure element is independent from the external breaker failure signal; this
element is used to detect arcing produced with an open breaker; if a higher current that the set level is detected during a
period that is longer than the set delay for the element (Internal Arc Delay), and the breaker is open, the corresponding
internal arc signal is issued (INTERNAL ARC).
HI
HI
HI
LO
LO
LO
Summary of Contents for F650
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