FlexBus
Freescale Semiconductor
20-5
for a longword write to an 8-bit port, FB_TSIZ[1:0] equals 00 for the first transaction and 01 for the next
three transactions. If bursting is used for longword write to an 8-bit port, FB_TSIZ[1:0] is driven to 00 for
the entire transfer.
20.2.8
Transfer Burst (FB_TBST)
Transfer burst indicates that a burst transfer is in progress as driven by the device. A burst transfer can be
two to 16 beats depending on FB_TSIZ[1:0] and the port size.
NOTE
When burst (FB_TBST = 0), transfer size is 16 bytes (FB_TSIZ[1:0] = 11)
and the address is misaligned within the 16-byte boundary, the external
device must be able to wrap around the address.
20.2.9
Transfer Acknowledge (FB_TA)
This signal indicates the external data transfer is complete. When the processor recognizes FB_TA during
a read cycle, it latches the data and then terminates the bus cycle. When the processor recognizes FB_TA
during a write cycle, the bus cycle is terminated.
If auto-acknowledge is disabled (CSCR
n
[AA] = 0), the external device drives FB_TA to terminate the bus
transfer; if auto-acknowledge is enabled (CSCR
n
[AA] = 1), FB_TA is generated internally after a
specified number of wait states, or the external device may assert external FB_TA before the wait-state
countdown, terminating the cycle early. The device negates FB_CS
n
one cycle after the last FB_TA
asserts. During read cycles, the peripheral must continue to drive data until FB_TA is recognized. For write
cycles, the processor continues driving data one clock after FB_CS
n
is negated.
The number of wait states is determined by CSCR
n
or the external FB_TA input. If the external FB_TA is
used, the peripheral has total control on the number of wait states.
NOTE
External devices should only assert FB_TA while the FB_CS
n
signal to the
external device is asserted.
Because this device shares the FlexBus signals with the PCI controller, this
signal tristates between bus cycles.
20.3
Memory Map/Register Definition
The following tables describe the registers and bit meanings for configuring chip-select operation.
shows the chip-select register memory map.
The actual number of chip select registers available depends upon the device and its pin configuration. If
the device does not support certain chip select signals or the pin is not configured for a chip-select function,
then that corresponding set of chip-select registers has no effect on an external pin.
NOTE
You must set CSMR0[V] before the chip select registers take effect.
Summary of Contents for MCF54455
Page 33: ...xxviii Freescale Semiconductor ...
Page 67: ...Freescale Semiconductor 1 ...
Page 125: ...Freescale Semiconductor 1 ...
Page 145: ...Enhanced Multiply Accumulate Unit EMAC 5 21 Freescale Semiconductor ...
Page 173: ...Cache 6 28 Freescale Semiconductor ...
Page 179: ...Static RAM SRAM 7 6 Freescale Semiconductor ...
Page 207: ...Power Management 9 16 Freescale Semiconductor ...
Page 323: ...Reset Controller Module 13 8 Freescale Semiconductor ...
Page 389: ...Pin Multiplexing and Control 16 44 Freescale Semiconductor ...
Page 575: ...PCI Bus Controller 22 58 Freescale Semiconductor ...
Page 600: ...Advanced Technology Attachment ATA Freescale Semiconductor 23 25 ...
Page 601: ...Freescale Semiconductor 1 ...
Page 842: ...I2 C Interface Freescale Semiconductor 33 16 ...
Page 843: ...Freescale Semiconductor 1 ...
Page 921: ...Revision History A 6 Freescale Semiconductor ...