Freescale Semiconductor MCF54455, Reference Manual

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Signal Descriptions
2-14 Freescale Semiconductor
2.3.7 Serial Boot Facility Signals
2.3.8 External Interrupt Signals
2.3.9 DMA Signals
2.3.10 Fast Ethernet Controller (FEC0 and FEC1) Signals
The following signals are used by the two Ethernet modules.
Table 2-9. SBF Signals
Signal Name Abbreviation Function I/O
SBF Chip Select SBF_CS Chip select used to access external SPI memory. O
SBF Clock SBF_CK 25 MHz clock source for external SPI memory. O
SBF Data In SBF_DI Data being driven by SPI memory. I
SBF Data Out SBF_DO Data out to SPI memory. SBF uses this output solely for the purpose
of issuing the SPI memory
READ
command. SBF does not write data
to SPI memory.
O
Table 2-10. External Interrupt Signals
Signal Name Abbreviation Function I/O
External Interrupts IRQ[7,4,3,1] External interrupt sources. I
Table 2-11. DMA Signals
Signal Name Abbreviation Function I/O
DMA Request DREQ[1:0] Asserted by an external device to request a DMA transfer. I
DMA Acknowledge DACK[1:0] Asserted by processor to indicate DMA request has been recognized. O
Table 2-12. Ethernet Module (FEC) Signals
Signal Name Abbreviation Function I/O
Management Data FEC n _MDIO Transfers control information between external PHY and the
media-access controller. Data is synchronous to FEC
n _MDC. Applies
to MII mode operation. This signal is an input after reset. When the
FEC is operated in 10Mbps 7-wire interface mode, this signal should
be connected to VSS.
I/O
Management Data
Clock FEC n _MDC In Ethernet mode, FEC n _MDC is an output clock that provides a
timing reference to PHY for data transfers on FEC n _MDIO signal.
Applies to MII mode operation.
O
Collision FEC n _COL Asserted upon collision detection and remains asserted while collision
persists. This signal is not defined for full-duplex mode. I
Carrier Receive Sense FEC n _CRS When asserted, indicates transmit or receive medium is not idle.
Applies to MII mode operation. I