Freescale Semiconductor MCF54455, Reference Manual

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SDRAM Controller (SDRAMC)
21-26 Freescale Semiconductor
21.5.1.9 Deep Power-Down (DPD) Mode
Deep power-down mode is available for mobile-DDR (LPDDR) devices to turn the SDRAM into its
lowest power state possible. Deep power-down mode eliminates power to the entire memory array. Array
data is not retained after the device enters deep power-down mode.
Deep power-down mode is entered by having all banks idle, then asserting CS and WE with RAS and CAS
negated at the rising edge of the clock, while CKE is negated. CKE must be negated during deep
power-down.
To exit deep power-down mode, CKE must be asserted. After exiting, the following sequence is needed to
enter a new command: maintain
NOP
input conditions for a minimum of 100

s, issue precharge commands
for all banks, issue eight or more auto-refresh commands. The values of the mode register and the extended
mode register are retained upon exiting deep power-down.
21.5.2 Read Clock Recovery (RCR) Block
The RCR block allows the external DDR memory devices to generate clock pulses (strobes) that define
the data valid window for each DDR data cycle. The RCR delay block compensates for each byte lane and
generates an internal read strobe targeted to the center of the data valid window provided by the external
DDR memories.
Figure 21-16 displays a simple timing diagram that illustrates the end result of the RCR delay.
Figure 21-16. Frequency Doubler Block Diagram
Dual data rate (DDR) memories provide data strobe (DQS) timing reference signals in parallel with read
data. However, these strobe signals cannot directly clock the data because the strobe edges are aligned with
the edges of the data valid window, not the center. The RCR delay module is responsible for delaying the
received DQS edges to achieve data-center alignment instead of data-edge alignment. There are two data
valid windows per memory clock period with DDR, so the nominal delay of read clocks from DQS is 1/4
memory clock period.
Memory
Clock
SD_DQS n
rd_clk
t
CLK
Don’t Care
t
CLK
t
CLK
/4
t
CLK
/4
t
CLK
/2 t
CLK
/2
t
CLK
/2 t
CLK
/2
t
CLK
/2 t
CLK
/2
(internal signal)