Freescale Semiconductor MCF54455, Reference Manual

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Signal Descriptions
Freescale Semiconductor 2-5
FEC0_COL PFEC0H4 — ULPI_DATA7 — I EVDD E1 AB7
FEC0_CRS PFEC0H0 — ULPI_DATA6 — I EVDD F1 AA7
FEC0_RXCLK PFEC0H3 — ULPI_DATA1 — I EVDD G1 AA8
FEC0_RXDV PFEC0H2 FEC0_RMII_
CRS_DV
— — I EVDD G2 Y8
FEC0_RXD[3:2] PFEC0L[3:2] — ULPI_DATA[5:4] — I EVDD G3, G4 AB9, Y9
FEC0_RXD1 PFEC0L1 FEC0_RMII_RXD1 — — I EVDD H1 W9
FEC0_RXD0 PFEC0H1 FEC0_RMII_RXD0 — — I EVDD H2 AB10
FEC0_RXER PFEC0L0 FEC0_RMII_RXER — — I EVDD H3 AA10
FEC0_TXCLK PFEC0H7 FEC0_RMII_
REF_CLK
— — I EVDD H4 Y10
FEC0_TXD[3:2] PFEC0L[7:6] — ULPI_DATA[3:2] — O EVDD J1, J2 W10, AB11
FEC0_TXD1 PFEC0L5 FEC0_RMII_TXD1 — — O EVDD J3 AA11
FEC0_TXD0 PFEC0H5 FEC0_RMII_TXD0 — — O EVDD J4 Y11
FEC0_TXEN PFEC0H6 FEC0_RMII_TXEN — — O EVDD K1 W11
FEC0_TXER PFEC0L4 — ULPI_DATA0 — O EVDD K2 AB12
FEC1
FEC1_MDC PFECI2C5 — ATA_DIOR — O EVDD — W20
FEC1_MDIO PFECI2C4 — ATA_DIOW — I/O EVDD — Y22
FEC1_COL PFEC1H4 — ATA_DATA7 — I EVDD — AB18
FEC1_CRS PFEC1H0 — ATA_DATA6 — I EVDD — AA18
FEC1_RXCLK PFEC1H3 — ATA_DATA5 — I EVDD — W14
FEC1_RXDV PFEC1H2 FEC1_RMII_
CRS_DV
ATA_DATA15 — I EVDD — AB15
FEC1_RXD[3:2] PFEC1L[3:2] — ATA_DATA[4:3] — I EVDD — AA15, Y15
FEC1_RXD1 PFEC1L1 FEC1_RMII_RXD1 ATA_DATA14 — I EVDD — AA17
FEC1_RXD0 PFEC1H1 FEC1_RMII_RXD0 ATA_DATA13 — I EVDD — Y17
FEC1_RXER PFEC1L0 FEC1_RMII_RXER ATA_DATA12 — I EVDD — W17
FEC1_TXCLK PFEC1H7 FEC1_RMII_
REF_CLK
ATA_DATA11 — I EVDD — AB19
FEC1_TXD[3:2] PFEC1L[7:6] — ATA_DATA[2:1] — O EVDD — Y19, W18
Table 2-2. MCF5445 x Signal Information and Muxing (continued)
Signal Name GPIO Alternate 1 Alternate 2
Pull-up (U)
1
Pu
ll-d
o
wn
(D)
Dir
ection
2
Vo
lt
a
g
e
Domain
MCF54450
MCF54451
256 MAPBGA
MCF54452
MCF54453
MCF54454
MCF54455
360 TEPBGA