Freescale Semiconductor MCF54455, Reference Manual

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PCI Bus Controller
22-52 Freescale Semiconductor
If a master does not initiate a transaction after its PCI_GNT aasserts, but deasserts PCI_REQ before the
16 clock timer expires, the arbiter deasserts PCI_GNT and re-arbitrates for the next transaction. The
master is not broken, and subsequent requests are acknowledged. This never-mind scenario is detrimental
to system performance, however, and not a recommended implementation.
When PACR[RA] is set, the reset arbiter bit in the PCI arbiter control register resets the arbitration logic,
ignore conditions, and timer. All status bits and corresponding interrupts are cleared. When the PACR[RA]
bit subsequently clears to enable arbitration, requests from any previously detected broken master once
again are recognized.
22.4.6 PCI Clock Scheme
The PCI controller requires a clock generated by an external source to input to the PCI_CLK signal to
generate an internal PCI clock. The device uses this clock as its VCO reference clock. The internal PLL
generates the internal PCI clock and all other clocks for the system. The PCIGSCR register reflects the
PLL programmed ratios.
The PCI bus clock to external PCI devices generates from an external PLL, while the internal PCI clock
generates from the Coldfire processor’s internal PLL. The internal bus clock is always faster than the PCI
clock.
Table 22-35. PCI and System Clock Frequencies
1
1
66 MHz operation is subject to system clocking restraints.
PCI_CLK
InternalBus
CLK
Core Clock
Internal
Bus
Multiplier
PCIGSCR[AUTODIV]
Internal to
PCICLK differential
33 MHz 66 MHz 133 MHz 2 0x2
66 MHz 66 MHz 133 MHz 1 0x1
20 MHz 100 MHz 200 MHz 5 0x5
25 MHz 100 MHz 200 MHz 4 0x4
50 MHz 100 MHz 200 MHz 2 0x2
33 MHz 100 MHz 200 MHz 3 0x3
66 MHz 100 MHz 200 MHz 3/2 0x6
26 MHz 133 MHz 266 MHz 5 0x5
33 MHz 133 MHz 266 MHz 4 0x4
44 MHz 133 MHz 266 MHz 3 0x3
66 MHz 133 MHz 266 MHz 2 0x2