Successful data transfer to PC host
Indicates a packet received by the device
Indicates a packet sent by the device
ISO OUT Token
Data
No handshake occurs. EP RX FIFO is empty after data sent. No EP interrupt
occurs. STAT_FLG is unchanged.
SOF Token
Reception of SOF causes SOF interrupt.
Note: An SOF interrupt is generated even if the SOF packet is corrupted.
SOF Interrupt
LH code for SOF ISR must fill all isochronous In EP TX FIFOs with new tranmit
data and pull new receive data from all isochronous Out EP RX FIFOs.
USB Device Controller
1602
SPNU503C – March 2018
Copyright © 2018, Texas Instruments Incorporated
Universal Serial Bus (USB)
29.3.6 Isochronous IN (CPU
→
USB HOST) Transactions
Isochronous IN transactions are USB transactions in which a given amount of data is transferred from the
USB device controller module device to the USB host every 1-ms USB frame. No handshaking is
provided.
The USB module provides double-buffering of data for ISO IN endpoints; the background FIFO is used as
the source of data for IN transactions to the ISO endpoint, and the foreground FIFO can be written to by
the CPU. When an IN transaction to an ISO endpoint occurs, the USB module sends all data found in the
endpoint background TX FIFO. The CPU is responsible for providing new data to the isochronous IN
endpoint foreground TX FIFO at each start of frame interrupt.
In response to the SOF interrupt, for each isochronous IN endpoint, CPU code selects the endpoint (via
the EP_NUM register), and then fills the endpoint TX FIFO (via the DATA register). Once all the transmit
data have been written to the FIFO, the CPU code must clear the EP_NUM.EP_SEL bit.
Because the USB transaction for the isochronous endpoint can occur at any time during the USB 1-ms
frame, the USB interface implements a double-buffering of the endpoint transmit data FIFO. The endpoint
includes two FIFOs, each of which is the length of the configured isochronous endpoint. At all times, one
of the two FIFOs is foreground and the other is background. The USB interface side of the USB module is
allowed to read from the background TX FIFO, and the CPU is allowed to write to the foreground TX
FIFO. The designations foreground and background are swapped, and the new background TX FIFO is
cleared at each start of frame (SOF). Because ISO endpoints implement double-buffering, ISO endpoints
do not control access to the FIFOs via a CTRL.SET_FIFO_EN bit; the CTRL.SET_FIFO_EN and the
STAT_FLG.FIFO_EN bits are not implemented for ISO IN endpoints.
shows the transaction phases associated with isochronous IN transactions and the SOF
transaction. No endpoint-specific interrupt to the CPU is generated as a result of an isochronous IN
transaction, and there is no handshake phase. The SOF transaction causes an SOF interrupt to the CPU;
it is assumed that the CPU refills the isochronous IN endpoint transmit FIFO at each SOF interrupt.
Figure 29-54. Isochronous IN Transaction Phases and Interrupts