SCI Control Registers
1355
SPNU503C – March 2018
Copyright © 2018, Texas Instruments Incorporated
Serial Communication Interface (SCI) Module
26.7.8 SCI Interrupt Vector Offset 0 (SCIINTVECT0)
and
illustrate this register.
Figure 26-15. SCI Interrupt Vector Offset 0 (SCIINTVECT0) [offset = 20h]
31
16
Reserved
R-0
15
4
3
0
Reserved
INTVECT0
R-0
R-0
LEGEND: R = Read only; -
n
= value after reset
Table 26-13. SCI Interrupt Vector Offset 0 (SCIINTVECT0) Field Descriptions
Bit
Field
Value
Description
31-4
Reserved
0
Reads return 0. Writes have no effect.
3-0
INVECT0
0-Fh
Interrupt vector offset for INT0. This register indicates the offset for interrupt line INT0. A read to
this register updates its value to the next highest priority pending interrupt in SCIFLR and clears
the flag in SCIFLR corresponding to the offset that was read. See
for a list of the
interrupts.
Note: The flags for the receive (SCIFLR[9]) and the transmit (SCIFLR[8]) interrupt cannot be
cleared by reading the corresponding offset vector in this register (see detailed description
in SCIFLR register).
26.7.9 SCI Interrupt Vector Offset 1 (SCIINTVECT1)
and
illustrate this register.
Figure 26-16. SCI Interrupt Vector Offset 1 (SCIINTVECT1) [offset = 24h]
31
16
Reserved
R-0
15
4
3
0
Reserved
INTVECT1
R-0
R-0
LEGEND: R = Read only; -
n
= value after reset
Table 26-14. SCI Interrupt Vector Offset 1 (SCIINTVECT1) Field Descriptions
Bit
Field
Value
Description
31-4
Reserved
0
Reads return 0. Writes have no effect.
3-0
INVECT1
0-Fh
Interrupt vector offset for INT1. This register indicates the offset for interrupt line INT1. A read to
this register updates its value to the next highest priority pending interrupt in SCIFLR and clears
the flag in SCIFLR corresponding to the offset that was read. See
for list of interrupts.
Note: The flags for the receive (SCIFLR[9]) and the transmit (SCIFLR[8]) interrupt cannot be
cleared by reading the corresponding offset vector in this register (see detailed description
in SCIFLR register).