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Remote Control
R&S
®
FPC
345
User Manual 1178.4130.02 ─ 07
ler if this is appropriately configured and can be further processed there. The
SRE
can
be set using the command
*SRE
and read using the command
*SRE?
.
Table 19-8: Meaning of the bits used in the status byte
Bit number
Meaning
0 to 1
Unused
2
Error Queue not empty
The bit is set when an entry is made in the error queue. If this bit is enabled by the SRE,
each entry of the error queue generates a service request. Thus an error can be recog-
nized and specified in greater detail by polling the error queue. The poll provides an
informative error message. This procedure is to be recommended since it considerably
reduces the problems involved with remote control.
3
QUEStionable status sum bit
The bit is set if an EVENt bit is set in the QUEStionable status register and the associ-
ated ENABle bit is set to 1.
A set bit indicates a questionable instrument status, which can be specified in greater
detail by polling the QUEStionable status register.
4
MAV bit
(message available)
The bit is set if a message is available in the output buffer which can be read. This bit
can be used to enable data to be automatically read from the instrument to the controller.
5
ESB bit
Sum bit of the event status register. It is set if one of the bits in the event status register
is set and enabled in the event status enable register.
Setting of this bit indicates a serious error which can be specified in greater detail by
polling the event status register.
6
MSS bit
(master status summary bit)
The bit is set if the instrument triggers a service request. This is the case if one of the
other bits of this register is set together with its mask bit in the service request enable
register SRE.
7
OPERation status register sum bit
The bit is set if an EVENt bit is set in the OPERation status register and the associated
ENABle bit is set to 1.
A set bit indicates that the instrument is just performing an action. The type of action can
be determined by polling the OPERation status register.
19.17.4
Event Status Register (ESR) and Event Status Enable Register
(ESE)
The
ESR
is defined in IEEE 488.2. It can be compared with the
EVENt
part of a SCPI
register. The event status register can be read out using command
*ESR?
.
The
ESE
is the associated
ENABle
part. It can be set using the command
*ESE
and
read using the command
*ESE?
.
Status Reporting System