ML51/ML54/ML56
Sep. 01, 2020
Page
530
of 719
Rev 2.00
ML
51
/ML
54
/ML
5
6 S
E
RI
E
S
TECHNI
CA
L
RE
F
E
R
E
NC
E
M
A
NU
A
L
ML51/M
L54
/M
L56
Series
Tec
hnical Reference
Manual
6.11.5 Register Description
SPInCR0
– Serial Peripheral Control Register0
Register
SFR Address
Reset Value
SPI0CR0
F3H, Page 0
0000_0000 b
SPI1CR0
F9H, Page 0
0000_0000 b
7
6
5
4
3
2
1
0
SSOE
SPIEN
LSBFE
MSTR
CPOL
CPHA
SPR1
SPR0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Bit
Name
Description
[7]
SSOE
Slave Select Output Enable
This bit is used in combination with the DISMODF (SPInSR.3) bit to determine the feature of
SS
̅̅̅̅
pin as shown in Table 17
–1. Slave Select Pin Configurations. This bit takes effect only
under MSTR = 1 and DISMODF = 1 condition.
0 =
SS
̅̅̅̅
functions as a general purpose I/O pin.
1 =
SS
̅̅̅̅
automatically goes low for each transmission when selecting external Slave device and
goes high during each idle state to de-select the Slave device.
[6]
SPIEN
SPI Enable
0 = SPI function Disabled.
1 = SPI function Enabled.
[5]
LSBFE
LSB First Enable
0 = The SPI data is transferred MSB first.
1 = The SPI data is transferred LSB first.
[4]
MSTR
Master Mode Enable
This bit switches the SPI operating between Master and Slave modes.
0 = The SPI is configured as Slave mode.
1 = The SPI is configured as Master mode.
[3]
CPOL
SPI Clock Polarity Select
CPOL bit determines the idle state level of the SPI clock. See Figure 6.11-4 SPI Clock
Formats.
0 = The SPI clock is low in idle state.
1 = The SPI clock is high in idle state.
[2]
CPHA
SPI Clock Phase Select
CPHA bit determines the data sampling edge of the SPI clock. See Figure 6.11-4 SPI Clock
Formats.
0 = The data is sampled on the first edge of the SPI clock.
1 = The data is sampled on the second edge of the SPI clock.
