ML51/ML54/ML56
Sep. 01, 2020
Page
177
of 719
Rev 2.00
ML
51
/ML
54
/ML
5
6 S
E
RI
E
S
TECHNI
CA
L
RE
F
E
R
E
NC
E
M
A
NU
A
L
ML51/M
L54
/M
L56
Series
Tec
hnical Reference
Manual
PnM2
– Port n Mode Select 2
Register
SFR Address
Reset Value
P0M2
B2H, Page 1
0000_0000 b
P1M2
B4H, Page 1
0000_0000 b
P2M2
B6H, Page 1
0000_0000 b
P3M2
C3H, Page 1
0000_0000 b
P4M2
BAH, Page 1
0000_0000 b
P5M2
BEH, Page 1
0000_0000 b
P6M2
85H, Page 2
0000_0000 b
7
6
5
4
3
2
1
0
PnM2_7
PnM2_6
PnM2_5
PnM2_4
PnM2_3
PnM2_2
PnM2_1
PnM2_0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Bit
Name
Description
[7:0]
PnM2[7:0]
Port 0 mode select 2
Note:
PnM1 and PnM2 [n:0~5] are used in combination to determine the I/O mode of each pin of P0. See Table