ML51/ML54/ML56
Sep. 01, 2020
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Rev 2.00
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ML51/M
L54
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L56
Series
Tec
hnical Reference
Manual
Bit
Name
Description
[2]
RB8
9th Received Bit
The bit identifies the logic level of the 9th received bit in serial port 0 Mode 2 or 3. In Mode 1,
RB8 is the logic level of the received stop bit. SM2 bit as logic 1 has restriction for exception.
RB8 is not used in Mode 0.
[1]
TI
Transmission Interrupt Flag
This flag is set by hardware when a data frame has been transmitted by the serial port 0 after
the 8th bit in Mode 0 or the last data bit in other modes. When the serial port 0 interrupt is
enabled, setting this bit causes the CPU to execute the serial port 0 interrupt service routine.
This bit should be cleared manually via software.
[0]
RI
Receiving Interrupt Flag
This flag is set via hardware when a data frame has been received by the serial port 0 after the
8th bit in Mode 0 or after sampling the stop bit in Mode 1, 2, or 3. SM2 bit as logic 1 has
restriction for exception. When the serial port 0 interrupt is enabled, setting this bit causes the
CPU to execute to the serial port 0 interrupt service routine. This bit should be cleared
manually via software.