ML51/ML54/ML56
Sep. 01, 2020
Page
287
of 719
Rev 2.00
ML
51
/ML
54
/ML
5
6 S
E
RI
E
S
TECHNI
CA
L
RE
F
E
R
E
NC
E
M
A
NU
A
L
ML51/M
L54
/M
L56
Series
Tec
hnical Reference
Manual
EIP1
– Extensive Interrupt Priority 1
Register
SFR Address
Reset Value
EIP1
FEH, Page 0
0000_0000 b
7
6
5
4
3
2
1
0
PSPI1
PDMA1
PDMA0
PSMC
PHF
PWKT
PT3
PS1
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Bit
Name
Description
[7]
PSPI1
SPI1 interrupt priority low bit
[6]
PDMA1
PDMA1 interrupt priority low bit
[5]
PDMA0
PDMA0 interrupt priority low bit
[4]
PSMC
SMC interrupt priority low bit
[3]
PHF
Hard fault interrupt priority low bit
[2]
PWKT
WKT interrupt priority low bit
[1]
PT3
Timer 3 interrupt priority low bit
[0]
PS1
Serial port 1 interrupt priority low bit
Note:
EIP1 is used in combination with the EIPH1 to determine the priority of each interrupt source. See Table 6.2-5 Interrupt
Priority Level Setting for correct interrupt priority configuration.
