ML51/ML54/ML56
Sep. 01, 2020
Page
596
of 719
Rev 2.00
ML
51
/ML
54
/ML
5
6 S
E
RI
E
S
TECHNI
CA
L
RE
F
E
R
E
NC
E
M
A
NU
A
L
ML51/M
L54
/M
L56
Series
Tec
hnical Reference
Manual
6.16.4 Functional Description
MISO
MOSI
SPCLK
SS
SIO/RX
SCLK/TX
SPI
SMC/UART
MUX
M2MSA[7:0], 0x0
PSSEL[2:0]
(PDMA_CR[6:4])
EN
(PDMA_CR[0])
IE
(PDMA_CR[2])
RUN
(PDMA_CR[1])
PDMA_MA[7:0],0x0
PDMA_CCNT[7:0]
+1
PDMA_CNT[7:0]
Done
PDMA_TSR
PDMA_INT
XRAM Address
Data Buffer
XRAM Data
PDMA Controller
PDMA_CRC
Figure 6.16-2 PDMA Controller Block Diagram
Operating Modes
6.16.4.1
Each PDMA channel behavior is not pre-defined, user must configure the channel service settings of
PSSEL[3:0] registers before starting the related PDMA channel operation.
User must set EN DMAnCR[0] bit to enable PDMA channel. Then write a valid source address to the
DMAnMA and DMAnBAH[3:0] register, a destination address to the MTMnDA and
DMAnBAH[7:4]register if use memory to memory, and a transfer count to the DMAnCNT register.
Next, trigger the RUN DMAnCR[1]. If the source address and destination are not in wrap around
mode, the PDMA will continue the transfer until DMAnCCNT counts down to 0. In wrap around mode,
when DMAnCCNT counts down to 0, the PDMA will reload DMAnCCNT and work around until user
clears EN DMAnCR[0] bit to disable PDMA channel.
A programing sequence example is described below.
SPI peripheral to XRAM memory
1. Configure DMAnCR register to set EN DMAnCR[0] bit to enable PDMA channel.
2. Set PSSEL[3:0] = 0001 SPI0 RX (, 0011 SPI1 RX, 0101 SPI0 TX or 0111 SPI1 TX) (DMAnCR
(n-1~2)) register to configure the channel service setting.
3. Set DMAnMA/DMAnBAH[3:0] registers to configure destination address.
4. Set DMAnCNT register to configure PDMA transfer count.
5. Set HIE/FIE DMAnCR[3]/[2] to enable PDMA transfer done interrupt (optional) then enable
global interrupt.
6. Set RUN DMAnCR[0] bit to enable PDMA transfer.
7. W
rite “0” to HDONE and FDONE DMAnTSR[1][0] bit to clear interrupt flag if PDMA transfer
done interrupt is generated.
8. Set RUN DMAnCR[0] bit to enable next PDMA transfer.
9. If an error occurs during the PDMA operation, the channel operation stops until user clears the
error condition, , and then clears the EN DMAnCR[0] bit to disable the PDMA channel, then
