ML51/ML54/ML56
Sep. 01, 2020
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Series
Tec
hnical Reference
Manual
6.4.2
External Interrupt Pins
Following is the MFP define ofr extneral interrupt pins.
Group
Pin Name
GPIO
MFP
Type
Description
INT0
INT0
P2.5
MFP15
I
External interrupt 0 input pin.
P0.6
MFP15
I
P4.6
MFP15
I
INT1
INT1
P2.4
MFP15
I
External interrupt 1 input pin.
P0.7
MFP15
I
P3.6
MFP15
I
P4.0
MFP15
I
Table 6.4-2 External Interrupt Pin Multi-Function Pin List
The external interrupt INT0 and INT1 can be used as interrupt sources. They are selectable to be
either edge or level triggered depending on bits IT0 (TCON.0) and IT1 (TCON.2). The bits IE0
(TCON.1) and IE1 (TCON.3) are the flags those are checked to generate the interrupt. In the edge
triggered mode, the INT0 or INT1 inputs are sampled every system clock cycle. If the sample is high in
one cycle and low in the next, then a high to low transition is detected and the interrupts request flag
IE0 or IE1 will be set. Since the external interrupts are sampled every system clock, they have to be
held high or low for at least one system clock cycle. The IE0 and IE1 are automatically cleared when
the interrupt service routine is called. If the level triggered mode is selected, then the requesting
source has to hold the pin low till the interrupt is serviced. The IE0 and IE1 will not be cleared by the
hardware on entering the service routine. In the level triggered mode, IE0 and IE1 follows the inverse
value of INT0 and INT1 pins. If interrupt pins continue to be held low even after the service routine is
completed, the processor will acknowledge another interrupt request from the same source. Both INT0
and INT1 can wake up the device from the Power-down mode.
