ML51/ML54/ML56
Sep. 01, 2020
Page
68
of 719
Rev 2.00
ML
51
/ML
54
/ML
5
6 S
E
RI
E
S
TECHNI
CA
L
RE
F
E
R
E
NC
E
M
A
NU
A
L
ML51/M
L54
/M
L56
Series
Tec
hnical Reference
Manual
QFN20 Package
4.1.2.10
ML51XB9AE Pin Function
QFN
20
1
2
3
4
5
10
9
8
7
6
1
5
1
4
1
3
1
2
1
1
16
17
18
19
20
V
SS
INT0 / CLKO / T0 / PWM0_CH0 / P4.6
V
DD
IC2 / UART0_TXD / SPI1_MISO / ACMP1_P3 / ACMP0_P3 / ADC_CH6 / P3.1
IC0 / UART0_RXD / SPI1_MOSI / P3.0
IN
T
0
/
T
0
/
U
A
R
T
2
_
T
X
D
/
P
W
M
0
_
C
H
0
/
I
2
C
0
_
S
C
L
/
A
D
C
_
C
H
0
/
P
2
.5
IN
T
1
/
T
1
/
U
A
R
T
2
_
R
X
D
/
P
W
M
0
_
C
H
1
/
I
2
C
0
_
S
D
A
/
A
D
C
_
C
H
1
/
P
2
.4
P
W
M
0
_
B
R
A
K
E
/
P
W
M
0
_
C
H
2
/
U
A
R
T
1
_
T
X
D
/
I
2
C
1
_
S
C
L
/
A
D
C
_
C
H
2
/
P
2
.3
P
W
M
0
_
C
H
3
/
U
A
R
T
1
_
R
X
D
/
I
2
C
1
_
S
D
A
/
A
D
C
_
C
H
3
/
P
2
.2
P
W
M
0
_
B
R
A
K
E
/
P
W
M
0
_
C
H
4
/
I
2
C
1
_
S
C
L
/
U
A
R
T
2
_
T
X
D
/
A
D
C
_
C
H
4
/
P
2
.1
nRESET
P0.0 / SPI1_MOSI / UART0_RXD / PWM0_CH5
P0.1 / SPI1_MISO / UART0_TXD / PWM0_CH4
P0.2 / SPI1_CLK / UART1_RXD / I2C1_SDA / PWM0_CH3
P0.3 / SPI1_SS / UART1_TXD / I2C1_SCL / STADC / PWM0_CH2
P
1
.7
/
U
A
R
T
0
_
R
X
D
P
4
.0
/
U
A
R
T
2
_
R
X
D
/
I
2
C
0
_
S
D
A
/
A
C
M
P
1
_
O
/
I
N
T
1
P
4
.1
/
U
A
R
T
2
_
T
X
D
/
I
2
C
0
_
S
C
L
/
A
C
M
P
0
_
O
P
5
.1
/
U
A
R
T
1
_
R
X
D
/
I
2
C
1
_
S
D
A
/
U
A
R
T
0
_
R
X
D
/
I
C
E
_
C
L
K
P
5
.0
/
U
A
R
T
1
_
T
X
D
/
I
2
C
1
_
S
C
L
/
U
A
R
T
0
_
T
X
D
/
I
C
E
_
D
A
T
Top transparent view
N/C
Figure 4.1-30 ML51XB9AE Multi Function Pin Assignment
Pin ML51XB9AE Pin Function
1
P2.5 / ADC_CH0 / I2C0_SCL / PWM0_CH0 / UART2_TXD / T0 / INT0
2
P2.4 / ADC_CH1 / I2C0_SDA / PWM0_CH1 / UART2_RXD / T1 / INT1
3
P2.3 / ADC_CH2 / I2C1_SCL / UART1_TXD / PWM0_CH2 / PWM0_BRAKE
4
P2.2 / ADC_CH3 / I2C1_SDA / UART1_RXD / PWM0_CH3
5
P2.1 / ADC_CH4 / UART2_TXD / I2C1_SCL / PWM0_CH4 / PWM0_BRAKE
6
P0.3 / SPI1_SS / UART1_TXD / I2C1_SCL / STADC / PWM0_CH2
7
P0.2 / SPI1_CLK / UART1_RXD / I2C1_SDA / PWM0_CH3
8
P0.1 / SPI1_MISO / UART0_TXD / PWM0_CH4