Nuvoton NuMicro ML51 Series, Technical Reference Manual

Page: 321 / 719

ML51/ML54/ML56
Sep. 01, 2020 Page 321 of 719 Rev 2.00
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6.2.4 Interrupt System
Interrupt Overview 6.2.4.1
The purpose of the interrupt is to make the software deal with unscheduled or asynchronous events.
The ML51/ML54/ML56 Series has a four-priority-level interrupt structure with 31 interrupt sources.
Each of the interrupt sources has an individual priority setting bits, interrupt vector and enable bit. In
addition, the interrupts can be globally enabled or disabled. When an interrupt occurs, the CPU is
expected to service the interrupt. This service is specified as an Interrupt Service Routine (ISR). The
ISR resides at a predetermined address as shown in Table 6.2-4 Interrupt Vectors. When the interrupt
occurs if enabled, the CPU will vector to the respective location depending on interrupt source,
execute the code at this location, stay in an interrupt service state until the ISR is done. Once an ISR
has begun, it can be interrupted only by a higher priority interrupt. The ISR should be terminated by a
return from interrupt instruction RETI. This instruction will force the CPU return to the instruction that
would have been next when the interrupt occurred.
Source
Vector
Addess
Vector
Number
Source
Vector
Address
Vector
Number
Reset 0000H - Serial port 1 interrupt 007BH 15
External interrupt 0 0003H 0 Timer 3 overflow 0083H 16
Timer 0 overflow 000BH 1 Self Wake-up Timer interrupt 008BH 17
External interrupt 1 0013H 2 CPU Hard Fault Interrupt 0093H 18
Timer 1 overflow 001BH 3 SMC0 Interrupt 009BH 19
Serial port 0 interrupt 0023H 4 PDMA0 Interrupt 00A3H 20
Timer 2 event 002BH 5 PDMA1 Interrupt 00ABH 21
R/W0 status/timer-out interrupt 0033H 6 SPI1 Interrupt 00B3H 22
Pin interrupt 003BH 7 ACMP Interrupt 00BBH 23
Brown-out detection interrupt 0043H 8 R/W1 status/timer-out interrupt 00C3H 24
SPI0 interrupt 004BH 9 PWM123 Interrupt 00CBH 25
WDT interrupt
0053H 10
Touch_Key interrupt
00D3H 26
ADC interrupt 005BH 11 SMC1 Interrupt 00DBH 27
Input capture interrupt 0063H 12 PDMA2 Interrupt 00E3H 28
PWM0 interrupt 006BH 13 PDMA3 Interrupt 00EBH 29
Fault Brake0 interrupt 0073H 14 RTC Interrupt 00F3H 30
Table 6.2-4 Interrupt Vectors
Enabling Interrupts 6.2.4.2
Each of individual interrupt sources can be enabled or disabled through the use of an associated