ML51/ML54/ML56
Sep. 01, 2020
Page
201
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Rev 2.00
ML
51
/ML
54
/ML
5
6 S
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RI
E
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TECHNI
CA
L
RE
F
E
R
E
NC
E
M
A
NU
A
L
ML51/M
L54
/M
L56
Series
Tec
hnical Reference
Manual
T2CON
– Timer 2 Control
Register
SFR Address
Reset Value
T2CON
C8H, All pages, Bit addressable
0000_0000 b
7
6
5
4
3
2
1
0
TF2
-
-
-
-
TR2
-
CM_RL2
R/W
-
-
-
-
R/W
-
R/W
Bit
Name
Description
[7]
TF2
Timer 2 Overflow Flag
This bit is set when Timer 2 overflows or a compare match occurs. If the Timer 2 interrupt and
the global interrupt are enable, setting this bit will make CPU execute Timer 2 interrupt service
routine. This bit is not automatically cleared via hardware and should be cleared via software.
[6:3]
-
Reserved
[2]
TR2
Timer 2 Run Control
0 = Timer 2 Disabled. Clearing this bit will halt Timer 2 and the current count will be preserved in
TH2 and TL2.
1 = Timer 2 Enabled.
[1]
-
Reserved
[0]
CM_RL2
Timer 2 Compare or Auto-Reload Mode Select
This bit selects Timer 2 functioning mode.
0 = Auto-reload mode.
1 = Compare mode.
