ML51/ML54/ML56
Sep. 01, 2020
Page
414
of 719
Rev 2.00
ML
51
/ML
54
/ML
5
6 S
E
RI
E
S
TECHNI
CA
L
RE
F
E
R
E
NC
E
M
A
NU
A
L
ML51/M
L54
/M
L56
Series
Tec
hnical Reference
Manual
6.6 Watchdog Timer (WDT)
The ML51/ML54/ML56 Series provides one Watchdog Timer (WDT). It can be configured as a time-
out reset timer to reset whole device. Once the device runs in an abnormal status or hangs up by
outward interference, a WDT reset recover the system. It provides a system monitor, which improves
the reliability of the system. Therefore, WDT is especially useful for system that is susceptible to noise,
power glitches, or electrostatic discharge. The WDT also can be configured as a general purpose
timer, of which the periodic interrupt serves as an event timer or a durational system supervisor in a
monitoring system, which is able to operate during Idle or Power-down mode. WDTEN[3:0]
(CONFIG4[7:4]) initialize the WDT to operate as a time-out reset timer or a general purpose timer.
The Watchdog time-out interval is determined by the formula
64
×
scalar
divider
clock
×
F
1
LIRC
, where
F
LIRC
is the frequency of internal 38.4 R/W oscillator. The following table shows an example of the
Watchdog time-out interval with different pre-scales.
WDPS.3
WDPS.2
WDPS.1
WDPS.0
Clock Divider Scale
WDT Time-Out Timing
[1]
0
0
0
0
1/1
1.66 ms
0
0
0
1
1/4
6.64 ms
0
0
1
0
1/8
13.31 ms
0
0
1
1
1/16
26.62 ms
0
1
0
0
1/32
53.25 ms
0
1
0
1
1/64
106.66 ms
0
1
1
0
1/128
213.12 ms
0
1
1
1
1/256
426.64 ms
1
0
0
0
1/512
853.28ms
1
0
0
1
1/1024
1706.56ms
1
0
1
0
1/2048
3413.12ms
Others
1/2048
3413.12ms
Note:
This is an approximate value since the deviation of LIRC.
Table 6.6-1 Watchdog Timer-out Interval Under Different Pre-scalars
Since the limitation of the maxima vaule of WDT timer delay. To wake up ML51/ML54/ML56 Series
from idle mode or Power-down mode suggest use WKT function see
Chapter 6.7
.
The WDT is implemented with a set of divider that divides the low-speed internal oscillator clock
nominal 38.4 R/W. The divider output is selectable and determines the time-out interval. When the
time-out interval is fulfilled, it will wake the system up from Idle or Power-down mode and an interrupt
event will occur if WDT interrupt is enabled. If WDT is initialized as a time-out reset timer, a system
reset will occur after a period of delay if without any software action.
6.6.1
Time-Out Reset Timer
When the CONFIG bits WDTEN[3:0] (CONFIG4[7:4]) is not FH, the WDT is initialized as a time-out
reset timer. If WDTEN[3:0] is not 5H, the WDT is allowed to continue running after the system enters
Idle or Power-down mode. Note that when WDT is initialized as a time-out reset timer, WDTR and
WIDPD has no function.
