ML51/ML54/ML56
Sep. 01, 2020
Page
620
of 719
Rev 2.00
ML
51
/ML
54
/ML
5
6 S
E
RI
E
S
TECHNI
CA
L
RE
F
E
R
E
NC
E
M
A
NU
A
L
ML51/M
L54
/M
L56
Series
Tec
hnical Reference
Manual
LCDCLK
– LCD Clock Control
Register
SFR Address
Reset Value
LCDCLK
FAH, Page 3
0000_0000 b
7
6
5
4
3
2
1
0
-
-
-
LCDCKS
DISP
LCDDIV[2:0]
-
-
-
R/W
R/W
R/W
Bit
Name
Description
[7:5]
-
Reserved
[4]
LCDCKS
LCD Clock Source Select
0 = LIRC/2
4
.
1 = LXT/2
4
.
[3]
DISP
DISP
The LCD display keeps display on or display off during chip power-down mode. If LXT is used
as the LCD clock source, user should turn on LXT first by software.
0 = Display off.
1 = Display on.
[2:0]
LCDDIV[2:0] LCD Clock Divider
000 = 1/1.
001 = 1/2.
010 = 1/4.
011 = 1/8.
100 = 1/16.
101 = 1/32.
Others = Reserved.