ML51/ML54/ML56
Sep. 01, 2020
Page
446
of 719
Rev 2.00
ML
51
/ML
54
/ML
5
6 S
E
RI
E
S
TECHNI
CA
L
RE
F
E
R
E
NC
E
M
A
NU
A
L
ML51/M
L54
/M
L56
Series
Tec
hnical Reference
Manual
PWMnCON1
– PWM Control 1
Register
SFR Address
Reset Value
PWM0CON1
DFH, Page 1
0000_0000 b
PWM1CON1
9DH, Page 2
0000_0000 b
PWM2CON1
C5H, Page 2
0000_0000 b
PWM3CON1
D5H, Page 2
0000_0000 b
7
6
5
4
3
2
1
0
PWMMOD[1:0]
GP
PWMTYP
FBINEN
PWMDIV[2:0]
R/W
R/W
R/W
R/W
R/W
Bit
Name
Description
[7:6]
PWMMOD[1:0]
PWM Mode Select
00 = Independent mode.
01 = Complementary mode.
10 = Synchronized mode.
11 = Reserved.
Independent Mode
Independent mode is enabled when PWMMOD[1:0] (PWMnCON1[7:6]) is [0:0]. It is the default mode
of PWM. PG0, PG1, PG2, PG3, PG4 and PG5 output PWM signals independently.
Complementary Mode with Dead-Time Insertion
Complementary mode is enabled when PWMMOD[1:0] = [0:1]. In this mode, PG0/2/4 output PWM
signals the same as the independent mode. However, PG1/3/5 output the out-phase PWM signals of
PG0/2/4 correspondingly, and ignore PG1/3/5 Duty register {PWMnH, PWMnL} (n:1/3/5). This mode
makes PG0/PG1 a PWM complementary pair and so on PG2/PG3 and PG4/PG5.
In a real motor application, a complementary PWM output always has a need of “dead-time” insertion
to prevent damage of the power switching device like GPIBs due to being active on simultaneously of
the upper and lower switches of the
half bridge, even in a “
μs” duration. For a power switch device
physically cannot switch on/off instantly. For the ML51/ML54/ML56 Series PWM, each PWM pair share a 9-bit
dead-time down-counter PWM0DTCNT used to produce the off time between two PWM signals in the same pair.
On implementation, a 0-to-1 signal edge delays after PWM0DTCNT timer underflows. The timing diagram
illustrates the complementary mode with dead-time insertion of PG0/PG1 pair. Pairs of PG2/PG3 and PG4/PG5
have the same dead-time circuit. Each pair has its own dead-time enabling bit in the field of PWMnDTEN [3:0].
Note
that the PWM0DTCNT and PWMnDTEN registers are all TA write protection. The dead-time control are
also valid only when the PWM is configured in its complementary mode.