ML51/ML54/ML56
Sep. 01, 2020
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ML51/M
L54
/M
L56
Series
Tec
hnical Reference
Manual
PIF
– Pin Interrupt Flags
Register
SFR Address
Reset Value
PIF
CAH, Page 0
0000_0000 b
7
6
5
4
3
2
1
0
PIF7
PIF6
PIF5
PIF4
PIF3
PIF2
PIF1
PIF0
R (level)
R/W (edge)
R (level)
R/W (edge)
R (level)
R/W (edge)
R (level)
R/W (edge)
R (level)
R/W (edge)
R (level)
R/W (edge)
R (level)
R/W (edge)
R (level)
R/W (edge)
Bit
Name
Description
[7:0]
PIFn
Pin Interrupt Channel n Flag
If the edge trigger is selected, this flag will be set by hardware if the channel n of pin interrupt
detects an enabled edge trigger. This flag should be cleared by software.
If the level trigger is selected, this flag follows the inverse of the input signal’s logic level on the
channel n of pin interrupt. Software cannot control it.
