ML51/ML54/ML56
Sep. 01, 2020
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ML51/M
L54
/M
L56
Series
Tec
hnical Reference
Manual
Note that the TH2 and TL2 are accessed separately. It is strongly recommended that user stops Timer
2 temporally by clearing TR2 bit before reading from or writing to TH2 and TL2. The free-running
reading or writing may cause unpredictable result.
Auto-Reload Mode
6.5.3.2
The Timer 2 is configured as auto-reload mode by clearing
CM/RL2
̅̅̅̅̅̅
. In this mode RCMP2H and
RCMP2L registers store the reload value. The contents in RCMP2H and RCMP2L transfer into TH2
and TL2 once the auto-reload event occurs if setting LDEN bit. The event can be the Timer 2 overflow
or one of the triggering event on any of enabled input capture channel depending on the LDTS[1:0]
(T2MOD[1:0]) selection. Note that once CAPCR (T2MOD.3) is set, an input capture event only clears
TH2 and TL2 without reloading RCMP2H and RCMP2L contents.
TF2
Timer 2 Interrupt
Pre-scalar
F
SYS
RCMP2H
T2DIV[2:0]
(T2MOD[6:4])
RCMP2L
TH2
TL2
00
01
10
11
CAPF0
CAPF1
CAPF2
LDEN
[1]
(T2MOD.7)
LDTS[1:0]
(T2MOD[1:0])
TR2
(T2CON.2)
Timer 2 Module
C0H
C0L
Noise
Filter
ENF0
(CAPCON2.4)
or
[00]
[01]
[10]
CAP0LS[1:0]
(CAPCON1[1:0])
CAPEN0
(CAPCON0.4)
CAPF0
Input Capture 0 Module
Input Capture 1 Module
Input Capture 2 Module
In
p
u
t
C
a
p
tu
re
F
la
g
s
C
A
P
F
[2
:0
]
CAPCR
[1]
(T2MOD.3)
CAPF0
CAPF1
CAPF2
Clear Timer 2
[1]
Once CAPCR and LDEN are both set, an input capture event only clears TH2 and TL2 without reloading RCMP2H and RCMP2L contents.
Input Capture Interrupt
CAPF0
CAPF1
CAPF2
CAP0
CAP1
CAP2
Figure 6.5-6 Timer 2 Auto-Reload Mode and Input Capture Module Functional Block Diagram
Compare Mode
6.5.3.3
Timer 2 can also be configured as the compare mode by setting
CM/RL2
̅̅̅̅̅̅
. In this mode RCMP2H and
RCMP2L registers serve as the compare value registers. As Timer 2 up counting, TH2 and TL2 match
RCMP2H and RCMP2L, TF2 (T2CON.7) will be set by hardware to indicate a compare match event.
Setting CMPCR (T2MOD.2) makes the hardware to clear Timer 2 counter as 0000H automatically
after a compare match has occurred.