ML51/ML54/ML56
Sep. 01, 2020
Page
246
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Rev 2.00
ML
51
/ML
54
/ML
5
6 S
E
RI
E
S
TECHNI
CA
L
RE
F
E
R
E
NC
E
M
A
NU
A
L
ML51/M
L54
/M
L56
Series
Tec
hnical Reference
Manual
CAPCON0
– Input Capture Control 0
Register
SFR Address
Reset Value
CAPCON0
E1H, Page 1
0000_0000b
7
6
5
4
3
2
1
0
-
CAPEN2
CAPEN1
CAPEN0
-
CAPF2
CAPF1
CAPF0
-
R/W
R/W
R/W
-
R/W
R/W
R/W
Bit
Name
Description
[7]
-
Reserved
[6]
CAPEN2
Input Capture 2 Enable
0 = Input capture channel 2 Disabled.
1 = Input capture channel 2 Enabled.
[5]
CAPEN1
Input Capture 1 Enable
0 = Input capture channel 1 Disabled.
1 = Input capture channel 1 Enabled.
[4]
CAPEN0
Input Capture 0 Enable
0 = Input capture channel 0 Disabled.
1 = Input capture channel 0 Enabled.
[3]
-
Reserved
[2]
CAPF2
Input Capture 2 Flag
This bit is set by hardware if the determined edge of input capture 2 occurs. This bit should
cleared by software.
[1]
CAPF1
Input Capture 1 Flag
This bit is set by hardware if the determined edge of input capture 1 occurs. This bit should
cleared by software.
[0]
CAPF0
Input Capture 0 Flag
This bit is set by hardware if the determined edge of input capture 0 occurs. This bit should
cleared by software.
