ML51/ML54/ML56
Sep. 01, 2020
Page
264
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Rev 2.00
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/ML
54
/ML
5
6 S
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E
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TECHNI
CA
L
RE
F
E
R
E
NC
E
M
A
NU
A
L
ML51/M
L54
/M
L56
Series
Tec
hnical Reference
Manual
EIP0
– Extensive Interrupt Priority
Register
SFR Address
Reset Value
EIP0
EFH, Page 0
0000_0000 b
7
6
5
4
3
2
1
0
PT2
PSPI0
PFB
PWDT
PPWM0
PCAP
PPI
PI2C0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Bit
Name
Description
[7]
PT2
Timer 2 interrupt priority low bit
[6]
PSPI0
SPI0 interrupt priority low bit
[5]
PFB
Fault Brake interrupt priority low bit
[4]
PWDT
WDT interrupt priority low bit
[3]
PPWM0
PWM interrupt priority low bit
[2]
PCAP
Input capture interrupt priority low bit
[1]
PPI
Pin interrupt priority low bit
[0]
PI2C0
R/W interrupt priority low bit
Note:
EIP0 is used in combination with the EIPH0 to determine the priority of each interrupt source. See Table 6.2-5
Interrupt Priority Level Setting for correct interrupt priority configuration.
