ML51/ML54/ML56
Sep. 01, 2020
Page
593
of 719
Rev 2.00
ML
51
/ML
54
/ML
5
6 S
E
RI
E
S
TECHNI
CA
L
RE
F
E
R
E
NC
E
M
A
NU
A
L
ML51/M
L54
/M
L56
Series
Tec
hnical Reference
Manual
ACMPSR
– Analog Comparator Status Register
Register
SFR Address
Reset Value
ACMPSR
D4H, Page 0
0000_0000 b
7
6
5
4
3
2
1
0
-
ACMP1O
ACMP1IF
ACMP0O
ACMP0IF
-
R
R/W
R
R/W
Bit
Name
Description
[7:4]
-
Reserved
[3]
ACMP1O
Comparator 1 Output
Synchronized to the PCLK to allow reading by software. Cleared when the comparator 1 is
disabled, i.e. ACMPEN (ACMPCR1[0]) is cleared to 0.
Note:
This bit is read only.
[2]
ACMP1IF
Comparator 1 Interrupt Flag
This bit is set by hardware whenever the comparator 1 output changes state. This will generate
an interrupt if ACMPIE (ACMPCR1[1]) is set to 1
Note:
Write “0” to clear this bit to 0.
[1]
ACMP0O
Comparator 0 Output
Synchronized to the PCLK to allow reading by software. Cleared when the comparator 0 is
disabled, i.e. ACMPEN (ACMPCR0[0]) is cleared to 0.
Note:
This bit is read only.
[0]
ACMP0IF
Comparator 0 Interrupt Flag
This bit is set by hardware whenever the comparator 0 output changes state. This will generate
an interrupt if ACMPIE (ACMPCR0[1]) is set to 1
Note:
Write “0” to clear this bit to 0.