ML51/ML54/ML56
Sep. 01, 2020
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Rev 2.00
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ML51/M
L54
/M
L56
Series
Tec
hnical Reference
Manual
ADCBAL
– ADC RAM Base Address Low Byte
Register
SFR Address
Reset Value
ADCBAL
CBH, Page 0
0000_0000 b
7
6
5
4
3
2
1
0
ADCBA[7:0]
R/W
Address: CBH, Page:0
Reset value: 0000 0000b
Bit
Name
Description
[7:0]
ADCBA[7:0]
ADC RAM Base Address (Low Byte)
The least significant 8 bits of RAM base address to store ADC continue sampling data.
RAM base address ADCBA[11:0] = { ADCBAH[3:0], ADCBAL[7:0]}
