ML51/ML54/ML56
Sep. 01, 2020
Page
318
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Rev 2.00
ML
51
/ML
54
/ML
5
6 S
E
RI
E
S
TECHNI
CA
L
RE
F
E
R
E
NC
E
M
A
NU
A
L
ML51/M
L54
/M
L56
Series
Tec
hnical Reference
Manual
Boot Select
6.2.3.6
RST pin reset
Brown-out reset
Software reset
Low voltage reset
Load
Reset and boot from LDROM
Reset and boot from APROM
CONFIG0.7
CHPCON.1
Watchdog timer reset
BS
CBS
BS = 0
BS = 1
Hard fault reset
Power-on reset
Figure 6.2-3 Boot Selecting Diagram
The ML51/ML54/ML56 Series provides user a flexible boot selection for variant application. The SFR
bit BS in CHPCON.1 determines MCU booting from APROM or LDROM after any source of reset. If
reset occurs and BS is 0, MCU will reboot from address 0000H of APROM. Else, the CPU will reboot
from address 0000H of LDROM. Note that BS is loaded from the inverted value of CBS bit in
CONFIG0.7 after all resets except software reset.
