ML51/ML54/ML56
Sep. 01, 2020
Page
326
of 719
Rev 2.00
ML
51
/ML
54
/ML
5
6 S
E
RI
E
S
TECHNI
CA
L
RE
F
E
R
E
NC
E
M
A
NU
A
L
ML51/M
L54
/M
L56
Series
Tec
hnical Reference
Manual
ScnIE
– SC Interrupt Enable Control Register
Register
SFR Address
Reset Value
SC0IE
DDH, Page 0
0000_0000 b
SC1IE
DDH, Page 2
0000_0000 b
7
6
5
4
3
2
1
0
-
-
-
ACERRIEN
BGTIEN
TERRIEN
TBEIEN
RDAIEN
-
-
-
R/W
R/W
R/W
R/W
R/W
Bit
Name
Description
[7:5]
-
Reserved
[4]
ACERRIEN
Auto Convention Error Interrupt Enable Bit
This field is used to enable auto-convention error interrupt.
0 = Auto-convention error interrupt Disabled.
1 = Auto-convention error interrupt Enabled.
[3]
BGTIEN
Block Guard Time Interrupt Enable Bit
This field is used to enable block guard time interrupt.
0 = Block guard time interrupt Disabled.
1 = Block guard time interrupt Enabled.
[2]
TERRIEN
Transfer Error Interrupt Enable Bit
This field is used to enable transfer error interrupt. The transfer error states is at SC0TSR
register
which
includes
receiver
break
error
BEF(SC0TSR[6]),
frame
error
FEF(SC0TSR[5]), parity error PEF(SC0TSR[4]), receiver buffer overflow error
RXOV(SC0TSR[0]) and transmit buffer overflow error TXOV(SC0TSR[2]).
0 = Transfer error interrupt Disabled.
1 = Transfer error interrupt Enabled.
[1]
TBEIEN
Transmit Buffer Empty Interrupt Enable Bit
This field is used to enable transmit buffer empty interrupt.
0 = Transmit buffer empty interrupt Disabled.
1 = Transmit buffer empty interrupt Enabled.
[0]
RDAIEN
Receive Data Reach Interrupt Enable Bit
This field is used to enable received data interrupt.
0 = Receive data interrupt Disabled.
1 = Receive data interrupt Enabled.
