ML51/ML54/ML56
Sep. 01, 2020
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ML51/M
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Series
Tec
hnical Reference
Manual
SDA
SCL
1-7
8
9
8
9
1-7
1-7
8
9
ADDRESS
W/R
ACK
S
P
DATA
ACK
DATA
ACK
Figure 6.12-6 Data Format of One I
2
C Transfer
During the data transaction period, the data on the SDA line should be stable during the high period of
the clock, and the data line can only change when SCL is low.
Acknowledge
6.12.3.3
Th
e
9
th
SCL pulse for any transferred byte is dedicated as an Acknowledge (ACK). It allows receiving
devices (which can be the master or slave) to respond back to the transmitter (which also can be the
master or slave) by pulling the SDA line low. The acknowledge-related clock pulse is generated by the
master. The transmitter should release control of SDA line during the acknowledge clock pulse. The
ACK is an active-low signal, pulling the SDA line low during the clock pulse high duty, indicates to the
transmitter that the device has received the transmitted data. Commonly, a receiver, which has been
addressed is requested to generate an ACK after each byte has been received. When a slave receiver
does not acknowledge (NACK) the slave address, the SDA line should be left high by the slave so that
the mater can generate a STOP or a repeated START condition.
If a slave-receiver does acknowledge the slave address, it switches itself to not addressed slave mode
and cannot receive any more data bytes. This slave leaves the SDA line high. The master should
generate a STOP or a repeated START condition.
If a master-receiver is involved in a transfer, because the master controls the number of bytes in the
transfer, it should signal the end of data to the slave-transmitter by not generating an acknowledge on
the last byte. The slave-transmitter then switches to not addressed mode and releases the SDA line to
allow the master to generate a STOP or a repeated START condition.
SDA output by transmitter
SCL from master
1
2
8
9
START
condition
SDA output by receiver
SDA = 0, acknowledge (ACK)
SDA = 1, not acknowledge (NACK)
Clock pulse for
acknowledge bit
Figure 6.12-7 Acknowledge Bit
Arbitration
6.12.3.4
A master may start a transfer only if the bus is free. It is possible for two or more masters to generate
a START condition. In these situations, an arbitration scheme takes place on the SDA line, while SCL
is high. During arbitration, the first of the com
peting master devices to place‘a’’1’ (high) on SDA while
another master transmits‘a’’0’ (low) switches off its data output stage because the level on the bus
does not match its own level. The arbitration lost master switches to the not addressed slave
immediately to detect its own slave address in the same serial transfer whether it is being addressed
