ML51/ML54/ML56
Sep. 01, 2020
Page
462
of 719
Rev 2.00
ML
51
/ML
54
/ML
5
6 S
E
RI
E
S
TECHNI
CA
L
RE
F
E
R
E
NC
E
M
A
NU
A
L
ML51/M
L54
/M
L56
Series
Tec
hnical Reference
Manual
PWMnCON1
– PWM Control 1
Register
SFR Address
Reset Value
PWM0CON1
DFH, Page 1
0000_0000 b
PWM1CON1
9DH, Page 2
0000_0000 b
PWM2CON1
C5H, Page 2
0000_0000 b
PWM3CON1
D5H, Page 2
0000_0000 b
7
6
5
4
3
2
1
0
PWMMOD[1:0]
GP
PWMTYP
FBINEN
PWMDIV[2:0]
R/W
R/W
R/W
R/W
R/W
Bit
Name
Description
[7:6]
PWMMOD[1:0]
PWM Mode Select
00 = Independent mode.
01 = Complementary mode.
10 = Synchronized mode.
11 = Reserved.
[5]
GP
Group Mode Enable
This bit enables the group mode. If enabled, the duty of first three pairs of PWM are
decided by PWM01H and PWM01L rather than their original duty Register Description.
0 = Group mode Disabled.
1 = Group mode Enabled.
[4]
PWMTYP
PWM Type Select
0 = Edge-aligned PWM.
1 = Center-aligned PWM.
[3]
FBINEN
FB Pin Input Enable
0 = PWM0 output Fault Braked by FB pin input Disabled.
1 = PWM0 output Fault Braked by FB pin input Enabled. Once an edge, which matches
FBINLS (PWM0FBD.6) selection, occurs on FB pin, PWM0CH0~5 output Fault Brake
data in PWMnFBD register. PWMRUN (PWM0CON0.7) will also be automatically
cleared by hardware. The PWM output resumes when PWM0RUN is set again.
Note:
This bit is only vaild in PWM0
