ML51/ML54/ML56
Sep. 01, 2020
Page
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Rev 2.00
ML
51
/ML
54
/ML
5
6 S
E
RI
E
S
TECHNI
CA
L
RE
F
E
R
E
NC
E
M
A
NU
A
L
ML51/M
L54
/M
L56
Series
Tec
hnical Reference
Manual
ADCCON1
– ADC Control 1
Register
SFR Address
Reset Value
ADCCON1
E1H, Page 0
0000_0000 b
7
6
5
4
3
2
1
0
-
-
HIE
CONT
ETGTYP[1:0]
ADCEX
ADCEN
-
-
R/W
R/W
R/W
R/W
R/W
Bit
Name
Description
[7:6]
-
Reserved
[5]
HIE
ADC Half Done Interrupt Enable
0 = ADC interrupt is not set while half of A/D conversions are complete in continue mode
1 = ADC interrupt is set while half of A/D conversions are complete in continue mode
[4]
CONT
ADC Continue Sampling Select
0 = ADC single sampling, ADC interrupt is set while an A/D conversion is completed
1 = ADC continue sampling. ADC interrupt is set while total A/D conversions are
completed
[3:2]
ETGTYP[1:0]
External Trigger Type Select
When ADCEX (ADCCON1.1) is set, these bits select which condition triggers ADC
conversion.
00 = Falling edge on PWM0/2/4 or STADC pin.
01 = Rising edge on PWM0/2/4 or STADC pin.
10 = Central point of a PWM period.
11 = End point of a PWM period.
Note that the central point interrupt or the period point interrupt is only available for PWM
center-aligned type.
[1]
ADCEX
ADC External Conversion Trigger Select
This bit to select the methods of triggering an A/D conversion.
0 = A/D conversion is started only via setting ADCS bit.
1 = A/D conversion is started via setting ADCS bit or by external trigger source depending
on ETGSEL[1:0] and ETGTYP[1:0]. Note that while ADCS is 1 (busy in converting), the
ADC will ignore the following external trigger until ADCS is hardware cleared.
[0]
ADCEN
ADC Enable
0 = ADC circuit off.
1 = ADC circuit on.
