ML51/ML54/ML56
Sep. 01, 2020
Page
189
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Rev 2.00
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TECHNI
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ML51/M
L54
/M
L56
Series
Tec
hnical Reference
Manual
I2CnCON
– I
2
C Control
Register
SFR Address
Reset Value
I2C0CON
C0H, All pages, Bit-addressable
0000_0000 b
I2C1CON
E8H, All pages
0000_0000 b
7
6
5
4
3
2
1
0
I
I2CEN
STA
STO
SI
AA
-
-
R/W
R/W
R/W
R/W
R/W
R/W
-
-
Bit
Name
Description
[7]
I
I2Cn Hold Time Extend Enable
0 = I
2
C DATA to SCL hold time extend disabled
1 = I
2
C DATA to SCL hold time extend enabled, extend 8 system clock
[6]
I2CEN
I2Cn Bus Enable
0 = I
2
C bus Disabled.
1 = I
2
C bus Enabled.
Before enabling the I
2
C, SCL and SDA port latches should be set to logic 1.
[5]
STA
START Flag
When STA is set, the I
2
C generates a START condition if the bus is free. If the bus is busy, the
I
2
C waits for a STOP condition and generates a START condition following.
If STA is set while the I
2
C is already in the master mode and one or more bytes have been
transmitted or received, the I
2
C generates a repeated START condition.
Note that STA can be set anytime even in a slave mode, but STA is not hardware
automatically cleared after START or repeated START condition has been detected. User
should take care of it by clearing STA manually.
[4]
STO
STOP Flag
When STO is set if the I
2
C is in the master mode, a STOP condition is transmitted to the bus.
STO is automatically cleared by hardware once the STOP condition has been detected on the
bus.
The STO flag setting is also used to recover the I
2
C device from the bus error state
(I2CnSTAT as 00H). In this case, no STOP condition is transmitted to the I
2
C bus.
If the STA and STO bits are both set and the device is original in the master mode, the I
2
C bus
will generate a STOP condition and immediately follow a START condition. If the device is in
slave mode, STA and STO simultaneous setting should be avoid from issuing illegal I
2
C
frames.