ML51/ML54/ML56
Sep. 01, 2020
Page
532
of 719
Rev 2.00
ML
51
/ML
54
/ML
5
6 S
E
RI
E
S
TECHNI
CA
L
RE
F
E
R
E
NC
E
M
A
NU
A
L
ML51/M
L54
/M
L56
Series
Tec
hnical Reference
Manual
SPInCR1
– Serial Peripheral Control Register1
Register
SFR Address
Reset Value
SPI0CR1
F3H, Page 1
0000_0000 b
SPI1CR1
FAH, Page 0
0000_0000 b
7
6
5
4
3
2
1
0
-
SPR3
SPR2
TXDMAEN
RXDMAEN
SPIS1
SPIS0
-
R/W
R/W
R/W
R/W
R/W
R/W
Bit
Name
Description
[7:6]
-
Reserved.
[5:4]
SPR[3:2]
SPI Clock Rate Select
These two bits select four grades of SPI clock divider. The clock rates below are illustrated
under F
SYS
= 24 MHz condition.
SPR3
SPR2
SPR1
SPR0
Divider
SPI clock rate
0
0
0
0
2
12M bit/s
0
0
0
1
4
6M bit/s
0
0
1
0
8
3M bit/s
0
0
1
1
16
1.5M bit/s
0
1
0
0
32
750k bit/s
0
1
0
1
64
375k bit/s
0
1
1
0
128
187k bit/s
0
1
1
1
256
93.7k bit/s
1
0
0
0
3
8M bit/s
1
0
0
1
6
4M bit/s
1
0
1
0
12
2M bit/s
1
0
1
1
24
1M bit/s
1
1
0
0
48
500k bit/s
1
1
0
1
96
250k bit/s
1
1
1
0
192
125k bit/s
1
1
1
1
384
62.5k bit/s
SPR[3:0] are valid only under Master mode (MSTR = 1). If under Slave mode, the clock will
automatically synchronize with the external clock on SPICLK pin from Master device up to
F
SYS
/4 communication speed.
