ML51/ML54/ML56
Sep. 01, 2020
Page
233
of 719
Rev 2.00
ML
51
/ML
54
/ML
5
6 S
E
RI
E
S
TECHNI
CA
L
RE
F
E
R
E
NC
E
M
A
NU
A
L
ML51/M
L54
/M
L56
Series
Tec
hnical Reference
Manual
PWMnPL
– PWM Period Low Byte
Register
SFR Address
Reset Value
PWM0PL
D9H, Page 1
0000_0000 b
PWM1PL
99H, Page 2
0000_0000 b
PWM2PL
C1H, Page 2
0000_0000 b
PWM3PL
D1H, Page 2
0000_0000 b
7
6
5
4
3
2
1
0
PWMnP[7:0]
R/W
Bit
Name
Description
[7:0]
PWMnP[7:0]
PWMn Period Low Byte
This byte with PWMnPH controls the period of the PWM generator signal.