ML51/ML54/ML56
Sep. 01, 2020
Page
127
of 719
Rev 2.00
ML
51
/ML
54
/ML
5
6 S
E
RI
E
S
TECHNI
CA
L
RE
F
E
R
E
NC
E
M
A
NU
A
L
ML51/M
L54
/M
L56
Series
Tec
hnical Reference
Manual
TMOD
– Timer 0 and 1 Mode
Register
SFR Address
Reset Value
TMOD
89H, All pages
0000_0000b
7
6
5
4
3
2
1
0
GATE
C/T
M1
M0
GATE
C/T
M1
M0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Bit
Name
Description
[7]
GATE
Timer 1 Gate Control
0 = Timer 1 will clock when TR1 is 1 regardless of INT1 logic level.
1 = Timer 1 will clock only when TR1 is 1 and INT1 is logic 1.
[6]
C/T
Timer 1 Counter/Timer Select
0 = Timer 1 is incremented by internal system clock.
1 = Timer 1 is incremented by the falling edge of the external pin T1.
[5]
M1
Timer 1 Mode Select
M1
M0
Timer 1 Mode
0
0
Mode 0: 13-bit Timer/Counter
0
1
Mode 1: 16-bit Timer/Counter
1
0
Mode 2: 8-bit Timer/Counter with auto-reload from TH1
1
1
Mode 3: Timer 1 halted
[4]
M0
Check with bit 5 description.
[3]
GATE
Timer 0 Gate Control
0 = Timer 0 will clock when TR0 is 1 regardless of INT0 logic level.
1 = Timer 0 will clock only when TR0 is 1 and INT0 is logic 1.
[2]
C/T
Timer 0 Counter/Timer Select
0 = Timer 0 is incremented by internal system clock.
1 = Timer 0 is incremented by the falling edge of the external pin T0.
[1]
M1
Timer 0 Mode Select
M1
M0
Timer 0 Mode
0
0
Mode 0: 13-bit Timer/Counter
0
1
Mode 1: 16-bit Timer/Counter
1
0
Mode 2: 8-bit Timer/Counter with auto-reload from TH0
1
1
Mode 3: TL0 as a 8-bit Timer/Counter and TH0 as a 8-bit Timer
[0]
M0
Check with bit 1 description