ML51/ML54/ML56
Sep. 01, 2020
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TECHNI
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ML51/M
L54
/M
L56
Series
Tec
hnical Reference
Manual
The I
2
C is considered free when both lines are high. Meanwhile, any device, which can operate as a
master can occupy the bus and generate one transfer after generating a START condition. The bus
now is considered busy before the transfer ends by sending a STOP condition. The master generates
all of the serial clock pulses and the START and STOP condition. However if there is no START
condition on the bus, all devices serve as not addressed slave. The hardware looks for its own slave
address or a General Call address. (The General Call address detection may be enabled or disabled
by GC (I2CnADDRx.0).) If the matched address is received, an interrupt is requested.
Every transaction on the I
2
C bus is 9 bits long, consisting of 8 data bits (MSB first) and a single
acknowledge bit. The number of bytes per transfer (defined as the time between a valid START and
STOP condition) is unrestricted but each byte has to be followed by an acknowledge bit. The master
device generates 8 clock pulse to send the 8-bit data. After the 8
th
falling edge of the SCL line, the
device outputting data on the SDA changes that pin to an input and reads in an acknowledge value on
the 9
th
clock pulse. After 9
th
clock pulse, the data receiving device can hold SCL line stretched low if
next receiving is not prepared ready. It forces the next byte transaction suspended. The data
transaction continues when the receiver releases the SCL line.
SDA
SCL
MSB
LSB
ACK
1
2
8
9
START
condition
STOP
condition
Figure 6.12-2 I
2
C Bus Protocol
START and STOP Condition
6.12.3.1
The protocol of the I
2
C bus defines two states to begin and end a transfer, START (S) and STOP (P)
conditions. A START condition is defined as a high-to-low transition on the SDA line while SCL line is
high. The STOP condition is defined as a low-to-high transition on the SDA line while SCL line is high.
A START or a STOP condition is always generated by the master and I
2
C bus is considered busy after
a START condition and free after a STOP condition. After issuing the STOP condition successful, the
original master device will release the control authority and turn back as a not addressed slave.
Consequently, the original addressed slave will become a not addressed slave. The I
2
C bus is free
and listens to next START condition of next transfer.
A data transfer is always terminated by a STOP condition generated by the master. However, if a
master still wishes to communicate on the bus, it can generate a repeated START (Sr) condition and
address the pervious or another slave without first generating a STOP condition. Various combinations
of read/write formats are then possible within such a transfer.
SDA
SCL
START
STOP
START
Repeated
START
STOP
Figure 6.12-3 START, Repeated START, and STOP Conditions
