ML51/ML54/ML56
Sep. 01, 2020
Page
235
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Rev 2.00
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TECHNI
CA
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NC
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M
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NU
A
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ML51/M
L54
/M
L56
Series
Tec
hnical Reference
Manual
PWMnCxL
– PWM0/1/2/3 Channel 0~5 Duty Low Byte n=0,1,2,3; x=0,1,2,3,4,5
7
6
5
4
3
2
1
0
PWMnCx [7:0], n=0,1,2,3; x=0,1,2,3,4,5
R/W
Bit
Name
Description
[7:0]
PWMnCx [7:0],
n=0,1,2,3;
x=0,1,2,3,4,5
PWMnCx Duty Low Byte
This byte with PWMnCxH controls the duty of the output signal PGx from PWM
generator.
Register
SFR Address
Reset Value
PWM0C0L
DAH, Page 1
0000_0000 b
PWM0C1L
DBH, Page 1
0000_0000 b
PWM0C2L
DCH, Page 1
0000_0000 b
PWM0C3L
DDH, Page 1
0000_0000 b
PWM0C4L
CCH, Page 1
0000_0000 b
PWM0C5L
CDH, Page 1
0000_0000 b
PWM1C0L
9AH, Page 2
0000_0000 b
PWM1C1L
9BH, Page 2
0000_0000 b
PWM2C0L
C2H, Page 2
0000_0000 b
PWM2C1L
C3H, Page 2
0000_0000 b
PWM3C0L
D2H, Page 2
0000_0000 b
PWM3C1L
D3H, Page 2
0000_0000 b
