ML51/ML54/ML56
Sep. 01, 2020
Page
270
of 719
Rev 2.00
ML
51
/ML
54
/ML
5
6 S
E
RI
E
S
TECHNI
CA
L
RE
F
E
R
E
NC
E
M
A
NU
A
L
ML51/M
L54
/M
L56
Series
Tec
hnical Reference
Manual
Bit
Name
Description
[3]
TXDMAEN
SPI TX DMA Enable
This bit enables the SPI TX operating by through PDMA transfer, TX data needs to be ready
in XRAM before SPI TX starting.
0 = SPI TX DMA Disabled
1 = SPI TX DMA Enabled
[2]
RXDMAEN
SPI RX DMA Enable
This bit enables the SPI RX operating by through PDMA transfer, RX data are saved in XRAM
after SPI RX operation.
0 = SPI RX DMA Disabled
1 = SPI RX DMA Enabled
[1:0]
SPIS[1:0]
SPI Interval Time Selection Between Adjacent Bytes
SPIS[1:0] and CPHA select eight grades of SPI interval time selection between adjacent
bytes. As below table:
CPHA
SPIS1
SPIS0
SPI clock
0
0
0
0.0
0
0
1
0.5
0
1
0
1.5
0
1
1
2.0
1
0
0
0.0
1
0
1
1.0
1
1
0
2.0
1
1
1
2.5
SPIS[1:0] are valid only under Master mode (MSTR = 1).
