ML51/ML54/ML56
Sep. 01, 2020
Page
440
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Rev 2.00
ML
51
/ML
54
/ML
5
6 S
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RI
E
S
TECHNI
CA
L
RE
F
E
R
E
NC
E
M
A
NU
A
L
ML51/M
L54
/M
L56
Series
Tec
hnical Reference
Manual
PWMnCxH
– PWM0/1/2/3 Channel 0~5 Duty High Byte n=0,1,2,3; x=0,1,2,3,4,5
7
6
5
4
3
2
1
0
PWMnCx [15:8], n=0,1,2,3; x=0,1,2,3,4,5
R/W
Bit
Name
Description
[7:0]
PWMnCx [15:8],
n=0,1,2,3;
x=0,1,2,3,4,5
PWMnCx Duty High Byte
This byte with PWMnCxL controls the duty of the output signal PGx from PWM
generator.
Register
SFR Address
Reset Value
PWM0C0H
D2H, Page 1
0000_0000 b
PWM0C1H
D3H, Page 1
0000_0000 b
PWM0C2H
D4H, Page 1
0000_0000 b
PWM0C3H
D5H, Page 1
0000_0000 b
PWM0C4H
C4H, Page 1
0000_0000 b
PWM0C5H
C5H, Page 1
0000_0000 b
PWM1C0H
8AH, Page 2
0000_0000 b
PWM1C1H
8BH, Page 2
0000_0000 b
PWM2C0H
BAH, Page 2
0000_0000 b
PWM2C1H
BBH, Page 2
0000_0000 b
PWM3C0H
CAH, Page 2
0000_0000 b
PWM3C1H
CBH, Page 2
0000_0000 b
