ML51/ML54/ML56
Sep. 01, 2020
Page
219
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Rev 2.00
ML
51
/ML
54
/ML
5
6 S
E
RI
E
S
TECHNI
CA
L
RE
F
E
R
E
NC
E
M
A
NU
A
L
ML51/M
L54
/M
L56
Series
Tec
hnical Reference
Manual
PWM0CON0
– PWM Control Register0
Register
SFR Address
Reset Value
PWM0CON0
D1H, Page 0
0000_0000 b
7
6
5
4
3
2
1
0
PWM0RUN
LOAD
PWMF
CLRPWM
-
-
-
-
R/W
R/W
R/W
R/W
-
-
-
-
Bit
Name
Description
[7]
PWM0RUN
PWM0 Run Enable
0 = PWM0 stays in idle.
1 = PWM0 starts running.
[6]
LOAD
PWM New Period and Duty Load
This bit is used to load period and duty Register Description in their buffer if new period or
duty value needs to be updated. The loading will act while a PWM period is completed.
The new period and duty affected on the next PWM cycle. After the loading is complete,
LOAD will be automatically cleared via hardware. The meaning of writing and reading
LOAD bit is different.
Writing:
0 = No effect.
1 = Load new period and duty in their buffers while a PWM period is completed.
Reading:
0 = A loading of new period and duty is finished.
1 = A loading of new period and duty is not yet finished.
[5]
PWMF
PWM Flag
This flag is set according to definitions of INTSEL[2:0] and INTTYP[1:0] in PWMnINTC.
This bit is cleared by software.
[4]
CLRPWM
Clear PWM Counter
Setting this bit clears the value of PWM 16-bit counter for resetting to 0000H. After the
counter value is cleared, CLRPWM will be automatically cleared via hardware. The
meaning of writing and reading CLRPWM bit is different.
Writing:
0 = No effect.
1 = Clearing PWM 16-bit counter.
Reading:
0 = PWM 16-bit counter is completely cleared.
1 = PWM 16-bit counter is not yet cleared.
[3:0]
-
Reserved
